Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	24860877	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

7653895

1

T1

38

T2

28

T3

451

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	31991325	1			T1	87		T2	6048		T3	1672
values[0x0]	261727	1			T1	38		T2	12		T3	33
values[0x1]	261720	1			T1	49		T2	20		T3	33

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	17510887	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

15003885

1

T1

70

T2

1554

T3

787

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	119953	1			T2	17		T3	8		T4	26
valid_sources[0x01]	123651	1			T2	10		T3	5		T6	8
valid_sources[0x02]	137003	1			T2	15		T3	4		T4	46
valid_sources[0x03]	119388	1			T2	2		T3	5		T6	11
valid_sources[0x04]	140130	1			T2	25		T3	6		T6	7
valid_sources[0x05]	200588	1			T2	15		T3	5		T6	5
valid_sources[0x06]	122952	1			T1	1		T2	5		T3	14
valid_sources[0x07]	112232	1			T2	29		T3	6		T6	6
valid_sources[0x08]	118677	1			T1	2		T2	10		T3	10
valid_sources[0x09]	202644	1			T2	19		T3	11		T6	13
valid_sources[0x0a]	120251	1			T1	1		T2	40		T3	6
valid_sources[0x0b]	119288	1			T1	1		T2	33		T3	7
valid_sources[0x0c]	166358	1			T1	1		T2	13		T3	9
valid_sources[0x0d]	141960	1			T1	3		T2	16		T3	6
valid_sources[0x0e]	143827	1			T2	16		T3	8		T6	16
valid_sources[0x0f]	107235	1			T1	1		T2	42		T3	7
valid_sources[0x10]	120457	1			T2	23		T3	13		T5	1
valid_sources[0x11]	116704	1			T3	7		T5	1		T6	10
valid_sources[0x12]	133554	1			T1	1		T2	15		T3	8
valid_sources[0x13]	113030	1			T2	11		T3	6		T6	15
valid_sources[0x14]	111316	1			T2	19		T3	10		T6	5
valid_sources[0x15]	114967	1			T2	2		T3	5		T6	4
valid_sources[0x16]	107471	1			T2	50		T3	8		T6	12
valid_sources[0x17]	116407	1			T1	1		T2	20		T3	9
valid_sources[0x18]	119175	1			T1	2		T2	34		T3	7
valid_sources[0x19]	121947	1			T1	1		T2	31		T3	6
valid_sources[0x1a]	119558	1			T1	1		T2	51		T3	7
valid_sources[0x1b]	112701	1			T2	20		T3	2		T6	5
valid_sources[0x1c]	313589	1			T1	2		T2	15		T3	4
valid_sources[0x1d]	121123	1			T2	5		T3	5		T5	1
valid_sources[0x1e]	120351	1			T2	34		T3	4		T4	3747
valid_sources[0x1f]	118640	1			T2	4		T3	11		T6	5
valid_sources[0x20]	119952	1			T2	32		T3	6		T4	814
valid_sources[0x21]	132613	1			T1	3		T2	8		T3	11
valid_sources[0x22]	224895	1			T1	1		T2	19		T3	10
valid_sources[0x23]	118236	1			T2	23		T3	5		T6	4
valid_sources[0x24]	116398	1			T1	2		T2	12		T3	7
valid_sources[0x25]	122020	1			T1	1		T2	55		T3	8
valid_sources[0x26]	139357	1			T2	38		T3	6		T5	1
valid_sources[0x27]	122021	1			T2	18		T3	8		T6	8
valid_sources[0x28]	123983	1			T2	4		T3	8		T6	6
valid_sources[0x29]	113580	1			T2	23		T3	7		T5	1
valid_sources[0x2a]	112867	1			T2	13		T3	10		T5	1
valid_sources[0x2b]	119943	1			T2	23		T3	4		T6	11
valid_sources[0x2c]	112760	1			T1	2		T2	11		T3	7
valid_sources[0x2d]	103455	1			T2	19		T3	4		T5	1
valid_sources[0x2e]	132507	1			T2	1		T3	6		T6	9
valid_sources[0x2f]	133158	1			T2	16		T3	9		T6	8
valid_sources[0x30]	144188	1			T1	1		T2	14		T3	6
valid_sources[0x31]	123257	1			T2	34		T3	8		T6	15
valid_sources[0x32]	117796	1			T2	36		T3	4		T5	1
valid_sources[0x33]	114369	1			T2	5		T3	7		T6	12
valid_sources[0x34]	109401	1			T2	24		T3	5		T6	13
valid_sources[0x35]	113970	1			T1	3		T2	30		T3	6
valid_sources[0x36]	112410	1			T2	17		T3	6		T6	10
valid_sources[0x37]	114700	1			T1	1		T2	5		T3	5
valid_sources[0x38]	105534	1			T2	23		T3	4		T6	8
valid_sources[0x39]	128962	1			T2	10		T3	7		T6	15
valid_sources[0x3a]	128180	1			T1	1		T3	9		T4	90
valid_sources[0x3b]	126893	1			T1	1		T2	33		T3	12
valid_sources[0x3c]	111838	1			T1	1		T2	33		T3	8
valid_sources[0x3d]	108915	1			T1	2		T2	33		T3	9
valid_sources[0x3e]	113202	1			T2	11		T3	5		T6	16
valid_sources[0x3f]	105153	1			T2	47		T3	5		T6	17
valid_sources[0x40]	144819	1			T1	1		T2	66		T3	6
valid_sources[0x41]	116518	1			T2	41		T3	7		T6	15
valid_sources[0x42]	127043	1			T1	1		T2	9		T3	7
valid_sources[0x43]	125959	1			T1	1		T2	15		T3	5
valid_sources[0x44]	124533	1			T2	54		T3	4		T6	12
valid_sources[0x45]	124840	1			T1	1		T2	22		T3	9
valid_sources[0x46]	125747	1			T2	32		T3	8		T6	11
valid_sources[0x47]	116072	1			T1	1		T2	42		T3	7
valid_sources[0x48]	135511	1			T1	2		T2	37		T3	8
valid_sources[0x49]	106878	1			T2	26		T3	5		T4	2
valid_sources[0x4a]	116260	1			T1	1		T2	12		T3	8
valid_sources[0x4b]	114689	1			T2	36		T3	12		T5	1
valid_sources[0x4c]	126311	1			T1	3		T2	21		T3	5
valid_sources[0x4d]	109438	1			T1	2		T2	27		T3	8
valid_sources[0x4e]	114772	1			T2	10		T3	5		T6	7
valid_sources[0x4f]	252598	1			T2	29		T3	13		T6	10
valid_sources[0x50]	118710	1			T2	22		T3	10		T5	1
valid_sources[0x51]	116207	1			T1	1		T2	29		T3	9
valid_sources[0x52]	112704	1			T2	17		T3	5		T6	9
valid_sources[0x53]	113053	1			T2	23		T3	4		T6	15
valid_sources[0x54]	113452	1			T1	2		T2	24		T3	8
valid_sources[0x55]	114134	1			T1	3		T2	29		T3	4
valid_sources[0x56]	127175	1			T1	1		T2	12		T3	3
valid_sources[0x57]	113602	1			T2	7		T3	6		T6	12
valid_sources[0x58]	118237	1			T1	2		T2	16		T3	8
valid_sources[0x59]	126360	1			T2	7		T3	3		T6	12
valid_sources[0x5a]	127578	1			T2	3		T3	10		T6	15
valid_sources[0x5b]	130369	1			T1	2		T2	22		T3	4
valid_sources[0x5c]	202670	1			T1	1		T2	27		T3	10
valid_sources[0x5d]	124125	1			T1	1		T2	14		T3	4
valid_sources[0x5e]	153333	1			T1	1		T2	21		T3	7
valid_sources[0x5f]	130294	1			T2	39		T3	14		T6	23
valid_sources[0x60]	108616	1			T2	55		T3	5		T6	6
valid_sources[0x61]	129556	1			T1	1		T2	52		T3	6
valid_sources[0x62]	127325	1			T1	2		T2	3		T3	8
valid_sources[0x63]	112713	1			T2	21		T3	7		T6	14
valid_sources[0x64]	112941	1			T2	25		T3	11		T6	7
valid_sources[0x65]	109405	1			T1	2		T2	4		T3	6
valid_sources[0x66]	132151	1			T2	24		T3	3		T6	13
valid_sources[0x67]	129842	1			T2	22		T3	10		T6	9
valid_sources[0x68]	146324	1			T1	2		T2	42		T3	7
valid_sources[0x69]	115993	1			T2	30		T3	5		T4	3066
valid_sources[0x6a]	112207	1			T1	2		T2	15		T3	5
valid_sources[0x6b]	114098	1			T2	10		T3	11		T6	14
valid_sources[0x6c]	104090	1			T1	2		T2	26		T3	5
valid_sources[0x6d]	130146	1			T1	1		T2	14		T3	9
valid_sources[0x6e]	274839	1			T1	2		T2	18		T3	4
valid_sources[0x6f]	122397	1			T2	34		T3	13		T6	12
valid_sources[0x70]	119107	1			T2	32		T3	7		T6	9
valid_sources[0x71]	122226	1			T1	2		T2	45		T3	5
valid_sources[0x72]	109282	1			T1	1		T2	11		T3	3
valid_sources[0x73]	116547	1			T2	51		T3	7		T6	15
valid_sources[0x74]	112985	1			T2	31		T3	6		T6	6
valid_sources[0x75]	118569	1			T1	2		T2	10		T3	11
valid_sources[0x76]	112371	1			T2	29		T3	7		T5	1
valid_sources[0x77]	117117	1			T1	2		T2	43		T3	4
valid_sources[0x78]	128662	1			T2	10		T3	9		T6	8
valid_sources[0x79]	123214	1			T2	25		T3	8		T6	9
valid_sources[0x7a]	117655	1			T2	20		T3	11		T6	4
valid_sources[0x7b]	114643	1			T1	1		T2	24		T3	2
valid_sources[0x7c]	118992	1			T1	1		T2	7		T3	6
valid_sources[0x7d]	124814	1			T1	1		T2	5		T3	7
valid_sources[0x7e]	108200	1			T2	15		T3	6		T4	26
valid_sources[0x7f]	121820	1			T1	2		T2	57		T3	3
valid_sources[0x80]	117020	1			T2	23		T3	6		T6	12

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7402157

1

T1

10

T2

11

T3

422

values[0x0]

all_enables

biggest_size

145641

1

T1

20

T2

9

T3

18

values[0x1]

all_enables

biggest_size

106097

1

T1

8

T2

8

T3

11