Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.48	100.00	100.00	93.91			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	302355431	0	0	0
ctrl_rd_A	302355431	1803	0	0
host_fifo_config_rd_A	302355431	4612	0	0
host_nack_handler_timeout_rd_A	302355431	1050	0	0
host_timeout_ctrl_rd_A	302355431	832	0	0
intr_enable_rd_A	302355431	3662	0	0
ovrd_rd_A	302355431	1905	0	0
target_fifo_config_rd_A	302355431	1095	0	0
target_id_rd_A	302355431	1361	0	0
target_timeout_ctrl_rd_A	302355431	1115	0	0
timeout_ctrl_rd_A	302355431	1228	0	0
timing0_rd_A	302355431	1144	0	0
timing1_rd_A	302355431	1253	0	0
timing2_rd_A	302355431	1142	0	0
timing3_rd_A	302355431	1171	0	0
timing4_rd_A	302355431	1041	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302355431	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302355431	1803	0	0
T95	1789	34	0	0
T96	2044	8	0	0
T97	5657	38	0	0
T98	4123	17	0	0
T99	2150	6	0	0
T100	2817	16	0	0
T101	2573	10	0	0
T102	1944	3	0	0
T103	7500	83	0	0
T104	1951	2	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302355431	4612	0	0
T12	198213	193	0	0
T19	22415	0	0	0
T25	0	458	0	0
T26	142330	0	0	0
T27	224573	0	0	0
T31	9422	0	0	0
T40	13853	0	0	0
T44	111079	0	0	0
T64	110080	0	0	0
T105	0	151	0	0
T106	0	141	0	0
T107	0	190	0	0
T108	0	143	0	0
T109	0	174	0	0
T110	0	116	0	0
T111	0	122	0	0
T112	0	146	0	0
T113	40154	0	0	0
T114	26959	0	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302355431	1050	0	0
T95	1789	12	0	0
T96	2044	17	0	0
T97	5657	18	0	0
T98	4123	17	0	0
T99	2150	6	0	0
T100	2817	16	0	0
T101	2573	6	0	0
T102	1944	6	0	0
T103	7500	34	0	0
T104	1951	5	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302355431	832	0	0
T95	1789	8	0	0
T96	2044	11	0	0
T97	5657	42	0	0
T98	4123	15	0	0
T99	2150	4	0	0
T100	2817	15	0	0
T101	2573	8	0	0
T102	1944	5	0	0
T103	7500	22	0	0
T104	1951	2	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302355431	3662	0	0
T25	134046	63	0	0
T95	0	56	0	0
T96	0	37	0	0
T97	0	41	0	0
T98	0	78	0	0
T99	0	7	0	0
T100	0	33	0	0
T115	0	25	0	0
T116	0	25	0	0
T117	0	27	0	0
T118	47789	0	0	0
T119	204942	0	0	0
T120	38517	0	0	0
T121	231547	0	0	0
T122	389959	0	0	0
T123	436772	0	0	0
T124	3641	0	0	0
T125	104510	0	0	0
T126	146734	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302355431	1905	0	0
T16	7223	0	0	0
T32	12251	0	0	0
T52	392459	0	0	0
T66	242535	0	0	0
T68	2461	77	0	0
T91	0	41	0	0
T127	0	35	0	0
T128	0	38	0	0
T129	0	45	0	0
T130	0	46	0	0
T131	0	19	0	0
T132	0	13	0	0
T133	0	46	0	0
T134	0	17	0	0
T135	128386	0	0	0
T136	122479	0	0	0
T137	144925	0	0	0
T138	183822	0	0	0
T139	39310	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302355431	1095	0	0
T95	1789	11	0	0
T96	2044	11	0	0
T97	5657	48	0	0
T98	4123	13	0	0
T99	2150	7	0	0
T100	2817	8	0	0
T101	2573	7	0	0
T102	1944	10	0	0
T103	7500	23	0	0
T104	1951	6	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302355431	1361	0	0
T95	1789	15	0	0
T96	2044	27	0	0
T97	5657	21	0	0
T98	4123	7	0	0
T99	2150	29	0	0
T100	2817	30	0	0
T101	2573	5	0	0
T102	1944	23	0	0
T103	7500	80	0	0
T104	1951	33	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302355431	1115	0	0
T95	1789	5	0	0
T96	2044	17	0	0
T97	5657	10	0	0
T98	4123	17	0	0
T99	2150	7	0	0
T100	2817	17	0	0
T101	2573	16	0	0
T102	1944	1	0	0
T103	7500	26	0	0
T140	9370	4	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302355431	1228	0	0
T95	1789	11	0	0
T96	2044	5	0	0
T97	5657	16	0	0
T98	4123	18	0	0
T99	2150	15	0	0
T100	2817	24	0	0
T101	2573	4	0	0
T102	1944	25	0	0
T103	7500	47	0	0
T104	1951	8	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302355431	1144	0	0
T95	1789	11	0	0
T96	2044	7	0	0
T97	5657	54	0	0
T98	4123	18	0	0
T99	2150	8	0	0
T100	2817	15	0	0
T101	2573	10	0	0
T102	1944	10	0	0
T103	7500	25	0	0
T104	1951	9	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302355431	1253	0	0
T95	1789	9	0	0
T96	2044	16	0	0
T97	5657	51	0	0
T98	4123	20	0	0
T99	2150	17	0	0
T100	2817	15	0	0
T101	2573	3	0	0
T102	1944	7	0	0
T103	7500	24	0	0
T104	1951	13	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302355431	1142	0	0
T96	2044	6	0	0
T97	5657	24	0	0
T98	4123	42	0	0
T99	2150	8	0	0
T100	2817	3	0	0
T101	2573	9	0	0
T102	1944	1	0	0
T103	7500	46	0	0
T104	1951	1	0	0
T140	9370	31	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302355431	1171	0	0
T95	1789	15	0	0
T96	2044	12	0	0
T97	5657	53	0	0
T98	4123	21	0	0
T99	2150	2	0	0
T100	2817	25	0	0
T101	2573	10	0	0
T102	1944	10	0	0
T103	7500	43	0	0
T104	1951	7	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302355431	1041	0	0
T95	1789	14	0	0
T96	2044	13	0	0
T97	5657	17	0	0
T98	4123	22	0	0
T99	2150	11	0	0
T100	2817	2	0	0
T101	2573	11	0	0
T102	1944	5	0	0
T103	7500	14	0	0
T104	1951	7	0	0