Unified Coverage Report :: Group :: i2c_env_pkg::i2c_fmt_fifo_cg

Group : i2c_env_pkg::i2c_fmt_fifo_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
85.19	85.19	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.fmt_fifo_cg	85.19	1	100	1	64	64

---

Group Instance : i2c_env_pkg.fmt_fifo_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
85.19	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.fmt_fifo_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	27	8	19	70.37

Variables for Group Instance i2c_env_pkg.fmt_fifo_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ack	2	0	2	100.00	100	1	1	0
cp_fbyte	5	0	5	100.00	100	1	1	0
cp_nakok	2	0	2	100.00	100	1	1	2
cp_rcont	2	0	2	100.00	100	1	1	2
cp_read	2	0	2	100.00	100	1	1	2
cp_start	2	0	2	100.00	100	1	1	2
cp_stop	2	0	2	100.00	100	1	1	2
nakok	2	0	2	100.00	100	1	1	2
rcont	2	0	2	100.00	100	1	1	2
read	2	0	2	100.00	100	1	1	2
start	2	0	2	100.00	100	1	1	2
stop	2	0	2	100.00	100	1	1	2

Crosses for Group Instance i2c_env_pkg.fmt_fifo_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack	27	8	19	70.37	100	1	1	0

Summary for Variable cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_ack

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

nack

116040

1

T2

14

T9

142

T12

125

ack

239

1

T21

1

T22

4

T23

3

---

Summary for Variable cp_fbyte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_fbyte

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	430	1			T9	1		T12	1		T13	2
high	24218	1			T9	42		T12	43		T13	23
med	43660	1			T2	4		T9	46		T12	42
sml	47513	1			T2	10		T9	53		T12	38
all_zero	458	1			T12	1		T14	3		T79	3

---

Summary for Variable cp_nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

57921

1

T2

7

T9

76

T12

59

auto[1]

58358

1

T2

7

T9

66

T12

66

---

Summary for Variable cp_rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

80001

1

T2

14

T9

99

T12

90

auto[1]

36278

1

T9

43

T12

35

T13

37

---

Summary for Variable cp_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

111996

1

T2

7

T9

142

T12

125

auto[1]

4283

1

T2

7

T13

12

T14

14

---

Summary for Variable cp_start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

109780

1

T2

7

T9

128

T12

109

auto[1]

6499

1

T2

7

T9

14

T12

16

---

Summary for Variable cp_stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

110360

1

T2

7

T9

128

T12

109

auto[1]

5919

1

T2

7

T9

14

T12

16

---

Summary for Variable nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

57921

1

T2

7

T9

76

T12

59

auto[1]

58358

1

T2

7

T9

66

T12

66

---

Summary for Variable rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

80001

1

T2

14

T9

99

T12

90

auto[1]

36278

1

T9

43

T12

35

T13

37

---

Summary for Variable read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

111996

1

T2

7

T9

142

T12

125

auto[1]

4283

1

T2

7

T13

12

T14

14

---

Summary for Variable start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

109780

1

T2

7

T9

128

T12

109

auto[1]

6499

1

T2

7

T9

14

T12

16

---

Summary for Variable stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

110360

1

T2

7

T9

128

T12

109

auto[1]

5919

1

T2

7

T9

14

T12

16

---

Summary for Cross cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Samples crossed: cp_fbyte start stop read rcont nakok cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	27	8	19	70.37	6
Automatically Generated Cross Bins	15	6	9	60.00	6
User Defined Cross Bins	12	2	10	83.33

Automatically Generated Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Element holes

cp_fbyte	start	stop	read	rcont	nakok	cp_ack	COUNT	AT LEAST	NUMBER	STATUS
[all_ones]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	*	[ack]	--	--	2
[all_zero]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	*	[ack]	--	--	2

Uncovered bins

cp_fbyte	start	stop	read	rcont	nakok	cp_ack	COUNT	AT LEAST	NUMBER	STATUS
[all_ones]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	[ack]	0	1	1
[all_zero]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	[ack]	0	1	1

Covered bins

cp_fbyte

start

stop

read

rcont

nakok

cp_ack

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

high

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

7

1

T25

1

T28

1

T257

1

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

1

1

T258

1

-

-

-

-

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

5

1

T259

1

T260

1

T261

1

med

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

8

1

T262

1

T263

1

T264

1

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

4

1

T25

1

T260

1

T265

1

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

4

1

T21

1

T28

1

T266

1

sml

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

7

1

T43

1

T28

1

T259

1

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

5

1

T267

1

T268

1

T269

1

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

7

1

T262

1

T264

1

T267

1

User Defined Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
read_address_byte	0	1	1
stop_after_start	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
data_byte	34056	1			T9	37		T12	36		T13	35
write_address_byte	6499	1			T2	7		T9	14		T12	16
read_with_ack	1053	1			T21	2		T22	7		T23	4
read_with_nack	3230	1			T2	7		T13	12		T14	14
stop_byte	5919	1			T2	7		T9	14		T12	16
write_address_byte_nak	6409	1			T2	7		T9	14		T12	16
data_byte_nack	116040	1			T2	14		T9	142		T12	125
stop_byte_nack	5875	1			T2	7		T9	14		T12	16
nakok_byte_nack	58247	1			T2	7		T9	66		T12	66
nakok_addr_byte_nack	3271	1			T2	3		T9	7		T12	10