Unified Coverage Report :: Group :: i2c_env_pkg::i2c_interrupts_cg

Group : i2c_env_pkg::i2c_interrupts_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.interrupts_cg	100.00	1	100	1	64	64

---

Group Instance : i2c_env_pkg.interrupts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.interrupts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	0	45	100.00

Variables for Group Instance i2c_env_pkg.interrupts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_acq_stretch	2	0	2	100.00	100	1	1	2
cp_acq_stretch_test	1	0	1	100.00	100	1	1	2
cp_acq_threshold	2	0	2	100.00	100	1	1	2
cp_acq_threshold_test	1	0	1	100.00	100	1	1	2
cp_cmd_complete	2	0	2	100.00	100	1	1	2
cp_cmd_complete_test	1	0	1	100.00	100	1	1	2
cp_fmt_threshold	2	0	2	100.00	100	1	1	2
cp_fmt_threshold_test	1	0	1	100.00	100	1	1	2
cp_host_timeout	2	0	2	100.00	100	1	1	2
cp_host_timeout_test	1	0	1	100.00	100	1	1	2
cp_nak	2	0	2	100.00	100	1	1	2
cp_nak_test	1	0	1	100.00	100	1	1	2
cp_rx_overflow	2	0	2	100.00	100	1	1	2
cp_rx_overflow_test	1	0	1	100.00	100	1	1	2
cp_rx_threshold	2	0	2	100.00	100	1	1	2
cp_rx_threshold_test	1	0	1	100.00	100	1	1	2
cp_scl_interference	2	0	2	100.00	100	1	1	2
cp_scl_interference_test	1	0	1	100.00	100	1	1	2
cp_sda_interference	2	0	2	100.00	100	1	1	2
cp_sda_interference_test	1	0	1	100.00	100	1	1	2
cp_sda_unstable	2	0	2	100.00	100	1	1	2
cp_sda_unstable_test	1	0	1	100.00	100	1	1	2
cp_stretch_timeout	2	0	2	100.00	100	1	1	2
cp_stretch_timeout_test	1	0	1	100.00	100	1	1	2
cp_tx_stretch	2	0	2	100.00	100	1	1	2
cp_tx_stretch_test	1	0	1	100.00	100	1	1	2
cp_tx_threshold	2	0	2	100.00	100	1	1	2
cp_tx_threshold_test	1	0	1	100.00	100	1	1	2
cp_unexp_stop	2	0	2	100.00	100	1	1	2
cp_unexp_stop_test	1	0	1	100.00	100	1	1	2

Summary for Variable cp_acq_stretch

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_acq_stretch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

708285

1

T1

3

T2

4

T3

3

auto[1]

432

1

T50

1

T68

1

T154

1

---

Summary for Variable cp_acq_stretch_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	1	0	1	100.00

Automatically Generated Bins for cp_acq_stretch_test

Excluded/Illegal bins

NAME	COUNT	STATUS
dis	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

150

1

T24

9

T132

2

T162

2

---

Summary for Variable cp_acq_threshold

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_acq_threshold

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

708017

1

T1

3

T2

4

T3

3

auto[1]

396

1

T174

1

T154

1

T24

13

---

Summary for Variable cp_acq_threshold_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	1	0	1	100.00

Automatically Generated Bins for cp_acq_threshold_test

Excluded/Illegal bins

NAME	COUNT	STATUS
dis	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

151

1

T24

7

T132

1

T162

2

---

Summary for Variable cp_cmd_complete

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_cmd_complete

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

145499

1

T1

3

T2

3

T3

3

auto[1]

563373

1

T2

1

T9

1

T12

1

---

Summary for Variable cp_cmd_complete_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	1	0	1	100.00

Automatically Generated Bins for cp_cmd_complete_test

Excluded/Illegal bins

NAME	COUNT	STATUS
dis	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

178

1

T24

6

T132

3

T162

5

---

Summary for Variable cp_fmt_threshold

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_fmt_threshold

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

78979

1

T1

1

T2

2

T3

1

auto[1]

625881

1

T1

2

T2

2

T3

2

---

Summary for Variable cp_fmt_threshold_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	1	0	1	100.00

Automatically Generated Bins for cp_fmt_threshold_test

Excluded/Illegal bins

NAME	COUNT	STATUS
dis	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

147

1

T24

7

T132

2

T162

3

---

Summary for Variable cp_host_timeout

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_host_timeout

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

708203

1

T1

3

T2

4

T3

3

auto[1]

427

1

T24

6

T162

2

T241

18

---

Summary for Variable cp_host_timeout_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	1	0	1	100.00

Automatically Generated Bins for cp_host_timeout_test

Excluded/Illegal bins

NAME	COUNT	STATUS
dis	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

172

1

T24

4

T132

1

T162

1

---

Summary for Variable cp_nak

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_nak

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

708461

1

T1

3

T2

4

T3

3

auto[1]

389

1

T24

16

T28

1

T276

1

---

Summary for Variable cp_nak_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	1	0	1	100.00

Automatically Generated Bins for cp_nak_test

Excluded/Illegal bins

NAME	COUNT	STATUS
dis	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

169

1

T24

6

T132

2

T162

4

---

Summary for Variable cp_rx_overflow

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rx_overflow

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

708150

1

T1

3

T2

4

T3

3

auto[1]

458

1

T24

25

T132

7

T162

1

---

Summary for Variable cp_rx_overflow_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	1	0	1	100.00

Automatically Generated Bins for cp_rx_overflow_test

Excluded/Illegal bins

NAME	COUNT	STATUS
dis	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

165

1

T24

8

T132

2

T162

1

---

Summary for Variable cp_rx_threshold

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rx_threshold

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

707873

1

T1

3

T2

4

T3

3

auto[1]

744

1

T13

11

T21

6

T155

13

---

Summary for Variable cp_rx_threshold_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	1	0	1	100.00

Automatically Generated Bins for cp_rx_threshold_test

Excluded/Illegal bins

NAME	COUNT	STATUS
dis	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

170

1

T24

6

T132

2

T162

3

---

Summary for Variable cp_scl_interference

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_scl_interference

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

704542

1

T1

3

T2

4

T3

3

auto[1]

470

1

T24

26

T132

1

T162

6

---

Summary for Variable cp_scl_interference_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	1	0	1	100.00

Automatically Generated Bins for cp_scl_interference_test

Excluded/Illegal bins

NAME	COUNT	STATUS
dis	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

180

1

T24

8

T132

1

T162

2

---

Summary for Variable cp_sda_interference

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sda_interference

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

704652

1

T1

3

T2

4

T3

3

auto[1]

430

1

T24

5

T132

6

T162

10

---

Summary for Variable cp_sda_interference_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	1	0	1	100.00

Automatically Generated Bins for cp_sda_interference_test

Excluded/Illegal bins

NAME	COUNT	STATUS
dis	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

154

1

T24

5

T132

1

T162

3

---

Summary for Variable cp_sda_unstable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sda_unstable

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

704586

1

T1

3

T2

4

T3

3

auto[1]

346

1

T24

12

T162

9

T241

12

---

Summary for Variable cp_sda_unstable_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	1	0	1	100.00

Automatically Generated Bins for cp_sda_unstable_test

Excluded/Illegal bins

NAME	COUNT	STATUS
dis	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

155

1

T24

8

T132

1

T162

2

---

Summary for Variable cp_stretch_timeout

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_stretch_timeout

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

684538

1

T1

3

T2

3

T3

3

auto[1]

20502

1

T2

1

T9

1

T12

1

---

Summary for Variable cp_stretch_timeout_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	1	0	1	100.00

Automatically Generated Bins for cp_stretch_timeout_test

Excluded/Illegal bins

NAME	COUNT	STATUS
dis	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

162

1

T24

6

T132

2

T162

1

---

Summary for Variable cp_tx_stretch

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_tx_stretch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

708306

1

T1

3

T2

4

T3

3

auto[1]

372

1

T24

22

T132

4

T162

7

---

Summary for Variable cp_tx_stretch_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	1	0	1	100.00

Automatically Generated Bins for cp_tx_stretch_test

Excluded/Illegal bins

NAME	COUNT	STATUS
dis	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

155

1

T24

7

T132

2

T162

3

---

Summary for Variable cp_tx_threshold

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_tx_threshold

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4716

1

T1

1

T2

2

T3

1

auto[1]

700053

1

T1

2

T2

2

T3

2

---

Summary for Variable cp_tx_threshold_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	1	0	1	100.00

Automatically Generated Bins for cp_tx_threshold_test

Excluded/Illegal bins

NAME	COUNT	STATUS
dis	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

143

1

T24

4

T132

1

T241

3

---

Summary for Variable cp_unexp_stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_unexp_stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

708362

1

T1

3

T2

4

T3

3

auto[1]

368

1

T24

16

T132

11

T162

7

---

Summary for Variable cp_unexp_stop_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	1	0	1	100.00

Automatically Generated Bins for cp_unexp_stop_test

Excluded/Illegal bins

NAME	COUNT	STATUS
dis	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

150

1

T24

5

T132

2

T162

2