Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	26656111	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

8164724

1

T1

158

T2

9848

T3

299

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	34251143	1			T1	574		T2	20321		T3	8970
values[0x0]	284630	1			T1	7		T2	72		T3	177
values[0x1]	285062	1			T1	14		T2	81		T3	142

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	18756129	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

16064706

1

T1

270

T2

12154

T3

4595

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	127571	1			T2	95		T5	59		T6	2
valid_sources[0x01]	128880	1			T2	121		T3	4550		T4	2
valid_sources[0x02]	116957	1			T1	21		T2	94		T4	19
valid_sources[0x03]	124146	1			T2	56		T4	1		T5	38
valid_sources[0x04]	124057	1			T1	6		T2	90		T4	13
valid_sources[0x05]	145720	1			T2	143		T4	9		T5	52
valid_sources[0x06]	123284	1			T2	83		T4	1		T5	33
valid_sources[0x07]	144663	1			T2	66		T4	1		T5	47
valid_sources[0x08]	134280	1			T1	3		T2	66		T5	42
valid_sources[0x09]	129182	1			T2	110		T4	18		T5	49
valid_sources[0x0a]	124140	1			T2	87		T4	7		T5	48
valid_sources[0x0b]	135460	1			T1	1		T2	93		T5	30
valid_sources[0x0c]	136358	1			T2	73		T4	27		T5	35
valid_sources[0x0d]	133377	1			T2	52		T5	39		T6	9
valid_sources[0x0e]	124008	1			T2	49		T5	45		T6	15
valid_sources[0x0f]	123802	1			T1	1		T2	86		T4	11
valid_sources[0x10]	237336	1			T1	3		T2	44		T4	13
valid_sources[0x11]	118253	1			T2	67		T4	1		T5	37
valid_sources[0x12]	111942	1			T2	67		T5	34		T6	10
valid_sources[0x13]	114893	1			T2	75		T5	58		T6	5
valid_sources[0x14]	126304	1			T2	93		T4	1		T5	33
valid_sources[0x15]	114468	1			T2	52		T4	7		T5	49
valid_sources[0x16]	130638	1			T2	65		T5	48		T6	2
valid_sources[0x17]	126891	1			T2	115		T4	16		T5	46
valid_sources[0x18]	124156	1			T2	101		T4	16		T5	61
valid_sources[0x19]	120938	1			T2	102		T4	25		T5	37
valid_sources[0x1a]	152143	1			T2	104		T5	52		T6	12
valid_sources[0x1b]	123841	1			T2	76		T3	50		T5	37
valid_sources[0x1c]	124686	1			T2	48		T3	34		T4	15
valid_sources[0x1d]	124076	1			T1	1		T2	81		T5	52
valid_sources[0x1e]	136551	1			T2	60		T3	10		T5	47
valid_sources[0x1f]	129745	1			T2	67		T4	10		T5	52
valid_sources[0x20]	143283	1			T2	74		T4	1		T5	40
valid_sources[0x21]	148458	1			T2	32		T4	25		T5	40
valid_sources[0x22]	133970	1			T2	71		T5	39		T7	8
valid_sources[0x23]	162984	1			T2	110		T4	2		T5	42
valid_sources[0x24]	123660	1			T1	23		T2	89		T4	4
valid_sources[0x25]	132261	1			T1	32		T2	59		T5	29
valid_sources[0x26]	127236	1			T2	62		T4	6		T5	46
valid_sources[0x27]	131629	1			T2	76		T4	16		T5	48
valid_sources[0x28]	121382	1			T2	76		T3	2		T4	6
valid_sources[0x29]	162373	1			T1	6		T2	103		T4	4
valid_sources[0x2a]	161825	1			T2	54		T4	16		T5	45
valid_sources[0x2b]	156393	1			T1	4		T2	87		T3	333
valid_sources[0x2c]	131324	1			T2	75		T5	43		T6	12
valid_sources[0x2d]	135606	1			T2	60		T5	46		T6	5
valid_sources[0x2e]	253400	1			T2	60		T4	5		T5	49
valid_sources[0x2f]	153926	1			T2	77		T4	1		T5	43
valid_sources[0x30]	164884	1			T2	108		T5	38		T6	5
valid_sources[0x31]	123021	1			T2	107		T4	13		T5	57
valid_sources[0x32]	160300	1			T2	86		T4	8		T5	49
valid_sources[0x33]	129541	1			T2	99		T4	19		T5	45
valid_sources[0x34]	120085	1			T2	82		T4	11		T5	47
valid_sources[0x35]	152174	1			T2	79		T4	1		T5	42
valid_sources[0x36]	132564	1			T2	95		T5	37		T6	4
valid_sources[0x37]	125469	1			T2	77		T5	46		T6	2
valid_sources[0x38]	132076	1			T1	13		T2	79		T4	15
valid_sources[0x39]	126580	1			T1	3		T2	48		T4	4
valid_sources[0x3a]	124022	1			T2	80		T4	6		T5	48
valid_sources[0x3b]	144949	1			T2	76		T4	1		T5	55
valid_sources[0x3c]	130270	1			T2	80		T4	5		T5	44
valid_sources[0x3d]	120511	1			T1	5		T2	162		T4	13
valid_sources[0x3e]	129969	1			T1	6		T2	80		T5	58
valid_sources[0x3f]	130175	1			T2	125		T5	39		T7	5
valid_sources[0x40]	153033	1			T2	53		T4	4		T5	47
valid_sources[0x41]	124593	1			T2	75		T5	47		T6	3
valid_sources[0x42]	120175	1			T2	73		T4	11		T5	36
valid_sources[0x43]	133621	1			T1	1		T2	90		T4	15
valid_sources[0x44]	126326	1			T1	7		T2	86		T5	45
valid_sources[0x45]	125097	1			T2	25		T5	45		T6	8
valid_sources[0x46]	117560	1			T2	45		T5	46		T6	9
valid_sources[0x47]	137138	1			T2	104		T4	2		T5	36
valid_sources[0x48]	138721	1			T2	65		T4	9		T5	29
valid_sources[0x49]	198988	1			T2	86		T4	20		T5	35
valid_sources[0x4a]	124586	1			T2	110		T4	16		T5	33
valid_sources[0x4b]	138073	1			T2	105		T3	4010		T5	34
valid_sources[0x4c]	121835	1			T2	35		T4	3		T5	45
valid_sources[0x4d]	136851	1			T1	21		T2	82		T4	12
valid_sources[0x4e]	121230	1			T2	56		T4	8		T5	50
valid_sources[0x4f]	140304	1			T2	82		T4	2		T5	60
valid_sources[0x50]	136956	1			T1	7		T2	78		T4	22
valid_sources[0x51]	132537	1			T1	4		T2	79		T4	1
valid_sources[0x52]	129948	1			T2	158		T3	94		T4	11
valid_sources[0x53]	167313	1			T2	65		T4	5		T5	44
valid_sources[0x54]	139116	1			T2	58		T3	34		T5	51
valid_sources[0x55]	144533	1			T1	5		T2	104		T4	14
valid_sources[0x56]	130855	1			T2	82		T5	42		T6	16
valid_sources[0x57]	121931	1			T2	50		T4	6		T5	43
valid_sources[0x58]	130045	1			T2	129		T4	3		T5	39
valid_sources[0x59]	130195	1			T1	4		T2	57		T5	53
valid_sources[0x5a]	151343	1			T2	132		T4	6		T5	48
valid_sources[0x5b]	128163	1			T2	81		T4	15		T5	44
valid_sources[0x5c]	143270	1			T2	91		T4	2		T5	54
valid_sources[0x5d]	130398	1			T1	4		T2	122		T5	41
valid_sources[0x5e]	132030	1			T2	55		T5	36		T6	4
valid_sources[0x5f]	121119	1			T2	50		T5	50		T6	44
valid_sources[0x60]	153518	1			T2	97		T5	38		T6	10
valid_sources[0x61]	122563	1			T2	70		T4	7		T5	29
valid_sources[0x62]	124833	1			T1	3		T2	118		T5	45
valid_sources[0x63]	151354	1			T2	17		T4	3		T5	49
valid_sources[0x64]	133824	1			T2	94		T4	4		T5	38
valid_sources[0x65]	135526	1			T2	42		T4	33		T5	55
valid_sources[0x66]	152113	1			T1	2		T2	112		T5	38
valid_sources[0x67]	123281	1			T2	103		T4	9		T5	35
valid_sources[0x68]	130064	1			T2	80		T5	42		T6	13
valid_sources[0x69]	126088	1			T2	96		T5	50		T6	20
valid_sources[0x6a]	131624	1			T2	79		T4	23		T5	37
valid_sources[0x6b]	113110	1			T2	91		T4	7		T5	45
valid_sources[0x6c]	121834	1			T1	1		T2	69		T5	33
valid_sources[0x6d]	139698	1			T1	9		T2	54		T4	2
valid_sources[0x6e]	122031	1			T2	98		T4	12		T5	55
valid_sources[0x6f]	122120	1			T1	6		T2	68		T4	2
valid_sources[0x70]	131568	1			T1	22		T2	85		T5	54
valid_sources[0x71]	162968	1			T2	103		T4	7		T5	41
valid_sources[0x72]	125505	1			T1	1		T2	60		T5	34
valid_sources[0x73]	141285	1			T2	95		T5	52		T6	15
valid_sources[0x74]	126112	1			T2	30		T4	2		T5	33
valid_sources[0x75]	138175	1			T2	72		T4	4		T5	50
valid_sources[0x76]	142914	1			T2	80		T4	1		T5	35
valid_sources[0x77]	254211	1			T1	5		T2	60		T5	38
valid_sources[0x78]	129897	1			T1	18		T2	28		T4	9
valid_sources[0x79]	150160	1			T1	10		T2	58		T4	7
valid_sources[0x7a]	136988	1			T2	100		T5	44		T7	7
valid_sources[0x7b]	134343	1			T2	53		T4	7		T5	48
valid_sources[0x7c]	130475	1			T2	60		T4	11		T5	52
valid_sources[0x7d]	129720	1			T2	127		T4	2		T5	40
valid_sources[0x7e]	121856	1			T1	7		T2	119		T4	4
valid_sources[0x7f]	122859	1			T2	52		T3	44		T5	51
valid_sources[0x80]	123836	1			T1	3		T2	114		T4	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7891111

1

T1

146

T2

9725

T3

202

values[0x0]

all_enables

biggest_size

158640

1

T1

6

T2

61

T3

66

values[0x1]

all_enables

biggest_size

114973

1

T1

6

T2

62

T3

31