Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.48	100.00	100.00	93.91			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	275967132	0	0	0
ctrl_rd_A	275967132	2624	0	0
host_fifo_config_rd_A	275967132	5250	0	0
host_nack_handler_timeout_rd_A	275967132	2110	0	0
host_timeout_ctrl_rd_A	275967132	1920	0	0
intr_enable_rd_A	275967132	4296	0	0
ovrd_rd_A	275967132	2746	0	0
target_fifo_config_rd_A	275967132	2021	0	0
target_id_rd_A	275967132	2400	0	0
target_timeout_ctrl_rd_A	275967132	2057	0	0
timeout_ctrl_rd_A	275967132	2285	0	0
timing0_rd_A	275967132	1841	0	0
timing1_rd_A	275967132	2089	0	0
timing2_rd_A	275967132	1957	0	0
timing3_rd_A	275967132	2035	0	0
timing4_rd_A	275967132	2067	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	275967132	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	275967132	2624	0	0
T107	1852	12	0	0
T108	13873	348	0	0
T109	26481	194	0	0
T110	2148	8	0	0
T111	8117	160	0	0
T112	1420	20	0	0
T113	3539	17	0	0
T114	5976	96	0	0
T115	2675	10	0	0
T116	6431	11	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	275967132	5250	0	0
T18	12443	0	0	0
T40	10219	0	0	0
T68	49197	0	0	0
T74	2449	0	0	0
T79	272037	55	0	0
T100	0	56	0	0
T117	0	197	0	0
T118	0	140	0	0
T119	0	203	0	0
T120	0	123	0	0
T121	0	131	0	0
T122	0	134	0	0
T123	0	268	0	0
T124	0	146	0	0
T125	72262	0	0	0
T126	38383	0	0	0
T127	902903	0	0	0
T128	23809	0	0	0
T129	1671	0	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	275967132	2110	0	0
T107	1852	9	0	0
T108	13873	143	0	0
T109	26481	233	0	0
T110	2148	6	0	0
T111	8117	52	0	0
T113	3539	33	0	0
T114	5976	110	0	0
T115	2675	1	0	0
T130	2375	4	0	0
T131	3130	9	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	275967132	1920	0	0
T107	1852	1	0	0
T108	13873	63	0	0
T109	26481	232	0	0
T110	2148	5	0	0
T111	8117	41	0	0
T112	1420	7	0	0
T113	3539	13	0	0
T114	5976	105	0	0
T115	2675	4	0	0
T116	6431	5	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	275967132	4296	0	0
T93	192442	0	0	0
T107	0	10	0	0
T108	0	841	0	0
T109	0	215	0	0
T110	0	12	0	0
T111	0	327	0	0
T113	0	27	0	0
T132	259526	14	0	0
T133	0	23	0	0
T134	0	24	0	0
T135	0	7	0	0
T136	1498	0	0	0
T137	192463	0	0	0
T138	19040	0	0	0
T139	47590	0	0	0
T140	155758	0	0	0
T141	12451	0	0	0
T142	14929	0	0	0
T143	229996	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	275967132	2746	0	0
T20	8221	0	0	0
T23	44644	0	0	0
T26	149900	0	0	0
T62	126965	0	0	0
T78	0	46	0	0
T144	1285	49	0	0
T145	0	55	0	0
T146	0	29	0	0
T147	0	42	0	0
T148	0	52	0	0
T149	0	41	0	0
T150	0	65	0	0
T151	0	14	0	0
T152	0	22	0	0
T153	11108	0	0	0
T154	48164	0	0	0
T155	88638	0	0	0
T156	63940	0	0	0
T157	153214	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	275967132	2021	0	0
T107	1852	10	0	0
T108	13873	114	0	0
T109	26481	192	0	0
T110	2148	4	0	0
T111	8117	55	0	0
T112	1420	5	0	0
T114	5976	93	0	0
T116	6431	3	0	0
T130	2375	18	0	0
T158	1920	11	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	275967132	2400	0	0
T107	1852	5	0	0
T108	13873	226	0	0
T109	26481	210	0	0
T110	2148	4	0	0
T111	8117	123	0	0
T113	3539	12	0	0
T114	5976	115	0	0
T115	2675	21	0	0
T116	6431	12	0	0
T158	1920	5	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	275967132	2057	0	0
T107	1852	6	0	0
T108	13873	96	0	0
T109	26481	225	0	0
T110	2148	5	0	0
T111	8117	60	0	0
T112	1420	1	0	0
T113	3539	27	0	0
T114	5976	82	0	0
T115	2675	5	0	0
T116	6431	4	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	275967132	2285	0	0
T107	1852	8	0	0
T108	13873	156	0	0
T109	26481	255	0	0
T110	2148	6	0	0
T111	8117	86	0	0
T112	1420	12	0	0
T113	3539	13	0	0
T114	5976	113	0	0
T115	2675	1	0	0
T116	6431	4	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	275967132	1841	0	0
T107	1852	10	0	0
T108	13873	109	0	0
T109	26481	221	0	0
T110	2148	3	0	0
T111	8117	63	0	0
T112	1420	4	0	0
T114	5976	113	0	0
T115	2675	3	0	0
T116	6431	8	0	0
T131	3130	2	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	275967132	2089	0	0
T107	1852	15	0	0
T108	13873	105	0	0
T109	26481	244	0	0
T111	8117	42	0	0
T113	3539	54	0	0
T114	5976	102	0	0
T115	2675	5	0	0
T116	6431	2	0	0
T130	2375	9	0	0
T158	1920	11	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	275967132	1957	0	0
T107	1852	14	0	0
T108	13873	131	0	0
T109	26481	201	0	0
T110	2148	7	0	0
T111	8117	44	0	0
T112	1420	3	0	0
T114	5976	86	0	0
T116	6431	20	0	0
T130	2375	11	0	0
T131	3130	3	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	275967132	2035	0	0
T107	1852	11	0	0
T108	13873	118	0	0
T109	26481	249	0	0
T110	2148	3	0	0
T111	8117	57	0	0
T113	3539	14	0	0
T114	5976	115	0	0
T115	2675	7	0	0
T130	2375	9	0	0
T158	1920	1	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	275967132	2067	0	0
T107	1852	10	0	0
T108	13873	106	0	0
T109	26481	224	0	0
T110	2148	12	0	0
T111	8117	47	0	0
T112	1420	7	0	0
T113	3539	7	0	0
T114	5976	116	0	0
T115	2675	10	0	0
T116	6431	8	0	0