Unified Coverage Report :: Group :: i2c_env_pkg::i2c_fmt_fifo_cg

Group : i2c_env_pkg::i2c_fmt_fifo_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
87.04	87.04	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.fmt_fifo_cg	87.04	1	100	1	64	64

---

Group Instance : i2c_env_pkg.fmt_fifo_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
87.04	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.fmt_fifo_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	27	7	20	74.07

Variables for Group Instance i2c_env_pkg.fmt_fifo_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ack	2	0	2	100.00	100	1	1	0
cp_fbyte	5	0	5	100.00	100	1	1	0
cp_nakok	2	0	2	100.00	100	1	1	2
cp_rcont	2	0	2	100.00	100	1	1	2
cp_read	2	0	2	100.00	100	1	1	2
cp_start	2	0	2	100.00	100	1	1	2
cp_stop	2	0	2	100.00	100	1	1	2
nakok	2	0	2	100.00	100	1	1	2
rcont	2	0	2	100.00	100	1	1	2
read	2	0	2	100.00	100	1	1	2
start	2	0	2	100.00	100	1	1	2
stop	2	0	2	100.00	100	1	1	2

Crosses for Group Instance i2c_env_pkg.fmt_fifo_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack	27	7	20	74.07	100	1	1	0

Summary for Variable cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_ack

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

nack

173678

1

T6

858

T7

858

T14

66

ack

240

1

T19

2

T21

3

T22

4

---

Summary for Variable cp_fbyte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_fbyte

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	645	1			T6	1		T7	3		T145	4
high	36459	1			T6	189		T7	203		T14	11
med	65849	1			T6	320		T7	353		T14	17
sml	70263	1			T6	345		T7	294		T14	36
all_zero	702	1			T6	3		T7	5		T14	2

---

Summary for Variable cp_nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

87024

1

T6

411

T7

421

T14

31

auto[1]

86894

1

T6

447

T7

437

T14

35

---

Summary for Variable cp_rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

118558

1

T6

590

T7

581

T14

53

auto[1]

55360

1

T6

268

T7

277

T14

13

---

Summary for Variable cp_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

169888

1

T6

846

T7

846

T14

49

auto[1]

4030

1

T6

12

T7

12

T14

17

---

Summary for Variable cp_start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

166837

1

T6

833

T7

833

T14

45

auto[1]

7081

1

T6

25

T7

25

T14

21

---

Summary for Variable cp_stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

167711

1

T6

834

T7

834

T14

48

auto[1]

6207

1

T6

24

T7

24

T14

18

---

Summary for Variable nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

87024

1

T6

411

T7

421

T14

31

auto[1]

86894

1

T6

447

T7

437

T14

35

---

Summary for Variable rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

118558

1

T6

590

T7

581

T14

53

auto[1]

55360

1

T6

268

T7

277

T14

13

---

Summary for Variable read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

169888

1

T6

846

T7

846

T14

49

auto[1]

4030

1

T6

12

T7

12

T14

17

---

Summary for Variable start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

166837

1

T6

833

T7

833

T14

45

auto[1]

7081

1

T6

25

T7

25

T14

21

---

Summary for Variable stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

167711

1

T6

834

T7

834

T14

48

auto[1]

6207

1

T6

24

T7

24

T14

18

---

Summary for Cross cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Samples crossed: cp_fbyte start stop read rcont nakok cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	27	7	20	74.07	5
Automatically Generated Cross Bins	15	5	10	66.67	5
User Defined Cross Bins	12	2	10	83.33

Automatically Generated Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Element holes

cp_fbyte	start	stop	read	rcont	nakok	cp_ack	COUNT	AT LEAST	NUMBER	STATUS
[all_ones]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	*	[ack]	--	--	2
[all_zero]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	*	[ack]	--	--	2

Uncovered bins

cp_fbyte	start	stop	read	rcont	nakok	cp_ack	COUNT	AT LEAST	NUMBER	STATUS
[all_ones]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	[ack]	0	1	1

Covered bins

cp_fbyte

start

stop

read

rcont

nakok

cp_ack

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

high

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

5

1

T242

1

T194

1

T243

1

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

1

1

T244

1

-

-

-

-

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

2

1

T245

1

T246

1

-

-

med

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

12

1

T22

1

T247

1

T248

1

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

6

1

T243

1

T249

1

T250

1

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

7

1

T194

1

T245

1

T251

1

sml

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

10

1

T252

1

T253

1

T194

1

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

2

1

T243

1

T251

1

-

-

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

7

1

T252

1

T253

1

T254

1

all_zero

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

1

1

T252

1

-

-

-

-

User Defined Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
read_address_byte	0	1	1
stop_after_start	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
data_byte	53222	1			T6	260		T7	265		T14	8
write_address_byte	7081	1			T6	25		T7	25		T14	21
read_with_ack	904	1			T14	1		T19	1		T21	1
read_with_nack	3126	1			T6	12		T7	12		T14	16
stop_byte	6207	1			T6	24		T7	24		T14	18
write_address_byte_nak	7001	1			T6	25		T7	25		T14	21
data_byte_nack	173678	1			T6	858		T7	858		T14	66
stop_byte_nack	6164	1			T6	24		T7	24		T14	18
nakok_byte_nack	86769	1			T6	447		T7	437		T14	35
nakok_addr_byte_nack	3503	1			T6	16		T7	13		T14	15