Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	29932357	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

8161861

1

T1

369

T2

244

T3

1570

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	37273740	1			T1	51937		T2	1074		T3	5649
values[0x0]	409959	1			T1	227		T2	8		T3	613
values[0x1]	410519	1			T1	251		T2	9		T3	567

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	20937803	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

17156415

1

T1

26246

T2

480

T3

3126

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	150515	1			T1	186		T2	3		T3	29
valid_sources[0x01]	149747	1			T1	174		T2	5		T3	19
valid_sources[0x02]	141014	1			T1	165		T2	4		T3	22
valid_sources[0x03]	139480	1			T1	177		T2	6		T3	25
valid_sources[0x04]	146123	1			T1	195		T2	2		T3	29
valid_sources[0x05]	168708	1			T1	223		T2	2		T3	33
valid_sources[0x06]	156783	1			T1	210		T2	4		T3	27
valid_sources[0x07]	134475	1			T1	224		T2	5		T3	22
valid_sources[0x08]	140938	1			T1	187		T2	4		T3	36
valid_sources[0x09]	138449	1			T1	202		T2	5		T3	26
valid_sources[0x0a]	147979	1			T1	174		T2	5		T3	26
valid_sources[0x0b]	138941	1			T1	210		T2	4		T3	22
valid_sources[0x0c]	153637	1			T1	199		T2	3		T3	23
valid_sources[0x0d]	138283	1			T1	205		T2	3		T3	26
valid_sources[0x0e]	166777	1			T1	202		T2	6		T3	21
valid_sources[0x0f]	147697	1			T1	210		T2	6		T3	27
valid_sources[0x10]	157476	1			T1	199		T2	3		T3	23
valid_sources[0x11]	142979	1			T1	196		T2	7		T3	26
valid_sources[0x12]	144531	1			T1	201		T2	8		T3	31
valid_sources[0x13]	142645	1			T1	201		T2	6		T3	22
valid_sources[0x14]	162563	1			T1	230		T2	2		T3	20
valid_sources[0x15]	139649	1			T1	203		T2	5		T3	18
valid_sources[0x16]	137091	1			T1	201		T2	7		T3	15
valid_sources[0x17]	153413	1			T1	235		T2	6		T3	21
valid_sources[0x18]	144088	1			T1	208		T2	11		T3	20
valid_sources[0x19]	136446	1			T1	214		T2	4		T3	19
valid_sources[0x1a]	160921	1			T1	189		T3	30		T6	194
valid_sources[0x1b]	145379	1			T1	204		T2	4		T3	21
valid_sources[0x1c]	151533	1			T1	206		T2	5		T3	21
valid_sources[0x1d]	140578	1			T1	228		T2	4		T3	22
valid_sources[0x1e]	142640	1			T1	210		T2	3		T3	27
valid_sources[0x1f]	141639	1			T1	228		T2	3		T3	21
valid_sources[0x20]	143557	1			T1	227		T2	7		T3	34
valid_sources[0x21]	138092	1			T1	193		T2	3		T3	34
valid_sources[0x22]	163055	1			T1	207		T2	5		T3	23
valid_sources[0x23]	149755	1			T1	210		T2	6		T3	25
valid_sources[0x24]	141540	1			T1	192		T2	4		T3	31
valid_sources[0x25]	159136	1			T1	223		T2	6		T3	23
valid_sources[0x26]	143292	1			T1	199		T2	8		T3	26
valid_sources[0x27]	150101	1			T1	224		T2	4		T3	38
valid_sources[0x28]	139778	1			T1	209		T2	8		T3	28
valid_sources[0x29]	140720	1			T1	202		T2	1		T3	31
valid_sources[0x2a]	164876	1			T1	222		T2	3		T3	28
valid_sources[0x2b]	154257	1			T1	217		T2	4		T3	24
valid_sources[0x2c]	145729	1			T1	179		T2	2		T3	30
valid_sources[0x2d]	155814	1			T1	185		T2	2		T3	37
valid_sources[0x2e]	151231	1			T1	228		T2	4		T3	36
valid_sources[0x2f]	136113	1			T1	222		T2	5		T3	27
valid_sources[0x30]	140980	1			T1	204		T2	4		T3	20
valid_sources[0x31]	136659	1			T1	227		T2	6		T3	29
valid_sources[0x32]	140426	1			T1	232		T2	1		T3	23
valid_sources[0x33]	147874	1			T1	179		T2	4		T3	32
valid_sources[0x34]	140867	1			T1	221		T2	6		T3	25
valid_sources[0x35]	162314	1			T1	216		T2	4		T3	21
valid_sources[0x36]	152065	1			T1	218		T2	4		T3	25
valid_sources[0x37]	162285	1			T1	206		T2	6		T3	34
valid_sources[0x38]	130738	1			T1	223		T2	5		T3	24
valid_sources[0x39]	134352	1			T1	184		T2	1		T3	29
valid_sources[0x3a]	265911	1			T1	195		T2	6		T3	21
valid_sources[0x3b]	167136	1			T1	199		T2	8		T3	24
valid_sources[0x3c]	134159	1			T1	202		T2	1		T3	24
valid_sources[0x3d]	127889	1			T1	217		T2	6		T3	22
valid_sources[0x3e]	144948	1			T1	197		T2	3		T3	11
valid_sources[0x3f]	145280	1			T1	239		T2	2		T3	28
valid_sources[0x40]	135231	1			T1	196		T2	2		T3	30
valid_sources[0x41]	137989	1			T1	200		T2	5		T3	19
valid_sources[0x42]	169595	1			T1	175		T2	1		T3	22
valid_sources[0x43]	153869	1			T1	214		T2	4		T3	25
valid_sources[0x44]	140181	1			T1	222		T2	4		T3	24
valid_sources[0x45]	131297	1			T1	217		T2	3		T3	42
valid_sources[0x46]	140870	1			T1	231		T2	4		T3	15
valid_sources[0x47]	146254	1			T1	224		T2	6		T3	29
valid_sources[0x48]	165058	1			T1	194		T2	5		T3	19
valid_sources[0x49]	139194	1			T1	208		T2	8		T3	35
valid_sources[0x4a]	144489	1			T1	223		T2	3		T3	23
valid_sources[0x4b]	142568	1			T1	210		T3	18		T6	181
valid_sources[0x4c]	166965	1			T1	218		T2	3		T3	40
valid_sources[0x4d]	155313	1			T1	211		T2	10		T3	30
valid_sources[0x4e]	136756	1			T1	210		T2	1		T3	21
valid_sources[0x4f]	133167	1			T1	196		T2	1		T3	32
valid_sources[0x50]	149133	1			T1	220		T2	4		T3	21
valid_sources[0x51]	146859	1			T1	209		T2	4		T3	34
valid_sources[0x52]	144058	1			T1	195		T2	5		T3	24
valid_sources[0x53]	159034	1			T1	195		T2	3		T3	27
valid_sources[0x54]	161948	1			T1	201		T2	5		T3	20
valid_sources[0x55]	154556	1			T1	201		T2	9		T3	30
valid_sources[0x56]	146203	1			T1	178		T2	3		T3	33
valid_sources[0x57]	150031	1			T1	200		T2	12		T3	22
valid_sources[0x58]	147880	1			T1	206		T2	6		T3	21
valid_sources[0x59]	147629	1			T1	206		T2	6		T3	28
valid_sources[0x5a]	138262	1			T1	234		T2	5		T3	27
valid_sources[0x5b]	156664	1			T1	196		T2	1		T3	20
valid_sources[0x5c]	134349	1			T1	189		T2	8		T3	30
valid_sources[0x5d]	142248	1			T1	182		T3	24		T6	271
valid_sources[0x5e]	150355	1			T1	225		T2	1		T3	28
valid_sources[0x5f]	174843	1			T1	193		T2	5		T3	27
valid_sources[0x60]	147832	1			T1	196		T2	1		T3	29
valid_sources[0x61]	150753	1			T1	196		T2	4		T3	27
valid_sources[0x62]	147791	1			T1	235		T2	7		T3	22
valid_sources[0x63]	168584	1			T1	184		T2	4		T3	27
valid_sources[0x64]	137497	1			T1	196		T2	3		T3	33
valid_sources[0x65]	152553	1			T1	207		T2	2		T3	29
valid_sources[0x66]	147062	1			T1	189		T2	4		T3	21
valid_sources[0x67]	147871	1			T1	211		T2	3		T3	32
valid_sources[0x68]	142660	1			T1	228		T2	9		T3	34
valid_sources[0x69]	141748	1			T1	229		T2	2		T3	29
valid_sources[0x6a]	135431	1			T1	189		T2	5		T3	30
valid_sources[0x6b]	129867	1			T1	181		T2	4		T3	23
valid_sources[0x6c]	159355	1			T1	217		T2	6		T3	26
valid_sources[0x6d]	136729	1			T1	208		T2	8		T3	28
valid_sources[0x6e]	150874	1			T1	206		T2	3		T3	34
valid_sources[0x6f]	148446	1			T1	187		T2	3		T3	32
valid_sources[0x70]	142685	1			T1	199		T2	6		T3	24
valid_sources[0x71]	145269	1			T1	193		T2	5		T3	31
valid_sources[0x72]	160798	1			T1	205		T2	3		T3	28
valid_sources[0x73]	132421	1			T1	197		T2	2		T3	31
valid_sources[0x74]	168775	1			T1	220		T2	3		T3	21
valid_sources[0x75]	156404	1			T1	198		T2	3		T3	38
valid_sources[0x76]	143833	1			T1	208		T2	3		T3	22
valid_sources[0x77]	155851	1			T1	207		T2	5		T3	25
valid_sources[0x78]	130315	1			T1	177		T2	9		T3	20
valid_sources[0x79]	155678	1			T1	199		T2	4		T3	27
valid_sources[0x7a]	137766	1			T1	186		T2	8		T3	32
valid_sources[0x7b]	167644	1			T1	216		T2	4		T3	34
valid_sources[0x7c]	153831	1			T1	185		T2	2		T3	23
valid_sources[0x7d]	139623	1			T1	227		T2	4		T3	34
valid_sources[0x7e]	154983	1			T1	188		T2	5		T3	27
valid_sources[0x7f]	147017	1			T1	202		T2	3		T3	21
valid_sources[0x80]	153873	1			T1	232		T3	27		T6	263

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7798417

1

T1

221

T2

230

T3

1133

values[0x0]

all_enables

biggest_size

215836

1

T1

92

T2

7

T3

267

values[0x1]

all_enables

biggest_size

147608

1

T1

56

T2

7

T3

170