Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.48	100.00	100.00	93.91			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	437346443	0	0	0
ctrl_rd_A	437346443	2022	0	0
host_fifo_config_rd_A	437346443	3500	0	0
host_nack_handler_timeout_rd_A	437346443	1109	0	0
host_timeout_ctrl_rd_A	437346443	1039	0	0
intr_enable_rd_A	437346443	3362	0	0
ovrd_rd_A	437346443	2068	0	0
target_fifo_config_rd_A	437346443	1087	0	0
target_id_rd_A	437346443	1452	0	0
target_timeout_ctrl_rd_A	437346443	1164	0	0
timeout_ctrl_rd_A	437346443	1387	0	0
timing0_rd_A	437346443	1175	0	0
timing1_rd_A	437346443	1119	0	0
timing2_rd_A	437346443	928	0	0
timing3_rd_A	437346443	1055	0	0
timing4_rd_A	437346443	1035	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437346443	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437346443	2022	0	0
T97	14434	279	0	0
T98	3616	5	0	0
T99	10986	41	0	0
T100	3653	28	0	0
T101	2381	3	0	0
T102	12183	51	0	0
T103	2936	7	0	0
T104	2160	9	0	0
T105	2033	29	0	0
T106	7769	70	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437346443	3500	0	0
T7	348994	85	0	0
T8	4309	0	0	0
T9	1433	0	0	0
T10	115237	0	0	0
T14	104138	0	0	0
T17	9706	0	0	0
T44	19888	0	0	0
T45	22451	0	0	0
T46	844966	0	0	0
T47	51383	0	0	0
T76	0	195	0	0
T107	0	202	0	0
T108	0	174	0	0
T109	0	153	0	0
T110	0	35	0	0
T111	0	178	0	0
T112	0	196	0	0
T113	0	125	0	0
T114	0	105	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437346443	1109	0	0
T97	14434	105	0	0
T98	3616	2	0	0
T99	10986	17	0	0
T100	3653	15	0	0
T101	2381	3	0	0
T102	12183	24	0	0
T103	2936	29	0	0
T104	2160	13	0	0
T105	2033	6	0	0
T106	7769	48	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437346443	1039	0	0
T97	14434	71	0	0
T98	3616	5	0	0
T99	10986	28	0	0
T100	3653	23	0	0
T101	2381	1	0	0
T102	12183	49	0	0
T103	2936	20	0	0
T104	2160	3	0	0
T105	2033	2	0	0
T106	7769	25	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437346443	3362	0	0
T97	0	471	0	0
T98	0	11	0	0
T99	0	25	0	0
T100	0	53	0	0
T115	713523	54	0	0
T116	0	12	0	0
T117	0	13	0	0
T118	0	5	0	0
T119	0	13	0	0
T120	0	17	0	0
T121	656645	0	0	0
T122	30114	0	0	0
T123	49330	0	0	0
T124	18322	0	0	0
T125	455284	0	0	0
T126	45147	0	0	0
T127	137534	0	0	0
T128	4754	0	0	0
T129	44106	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437346443	2068	0	0
T26	939045	0	0	0
T54	59313	0	0	0
T55	16165	0	0	0
T65	158941	0	0	0
T91	1982	55	0	0
T92	0	36	0	0
T94	203051	0	0	0
T130	0	59	0	0
T131	0	70	0	0
T132	0	46	0	0
T133	0	54	0	0
T134	0	44	0	0
T135	0	48	0	0
T136	0	57	0	0
T137	0	34	0	0
T138	289402	0	0	0
T139	110550	0	0	0
T140	40877	0	0	0
T141	1748	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437346443	1087	0	0
T97	14434	110	0	0
T99	10986	40	0	0
T100	3653	8	0	0
T101	2381	5	0	0
T102	12183	16	0	0
T103	2936	16	0	0
T104	2160	2	0	0
T105	2033	3	0	0
T106	7769	28	0	0
T142	3490	3	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437346443	1452	0	0
T97	14434	227	0	0
T98	3616	9	0	0
T99	10986	20	0	0
T100	3653	22	0	0
T101	2381	7	0	0
T102	12183	16	0	0
T103	2936	20	0	0
T104	2160	5	0	0
T105	2033	12	0	0
T106	7769	41	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437346443	1164	0	0
T97	14434	118	0	0
T99	10986	46	0	0
T100	3653	24	0	0
T101	2381	1	0	0
T102	12183	46	0	0
T103	2936	14	0	0
T104	2160	1	0	0
T105	2033	1	0	0
T106	7769	20	0	0
T142	3490	3	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437346443	1387	0	0
T97	14434	181	0	0
T98	3616	5	0	0
T99	10986	30	0	0
T100	3653	26	0	0
T101	2381	7	0	0
T102	12183	41	0	0
T103	2936	32	0	0
T104	2160	5	0	0
T105	2033	10	0	0
T106	7769	61	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437346443	1175	0	0
T97	14434	129	0	0
T98	3616	9	0	0
T99	10986	24	0	0
T100	3653	12	0	0
T101	2381	8	0	0
T102	12183	15	0	0
T103	2936	21	0	0
T104	2160	6	0	0
T105	2033	5	0	0
T106	7769	44	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437346443	1119	0	0
T97	14434	117	0	0
T99	10986	27	0	0
T100	3653	9	0	0
T101	2381	2	0	0
T102	12183	32	0	0
T103	2936	32	0	0
T104	2160	9	0	0
T105	2033	6	0	0
T106	7769	14	0	0
T143	7243	55	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437346443	928	0	0
T97	14434	112	0	0
T99	10986	17	0	0
T100	3653	13	0	0
T102	12183	14	0	0
T103	2936	15	0	0
T104	2160	7	0	0
T105	2033	9	0	0
T106	7769	10	0	0
T142	3490	5	0	0
T143	7243	67	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437346443	1055	0	0
T97	14434	91	0	0
T99	10986	23	0	0
T100	3653	21	0	0
T101	2381	15	0	0
T102	12183	27	0	0
T103	2936	16	0	0
T104	2160	4	0	0
T105	2033	10	0	0
T106	7769	22	0	0
T142	3490	36	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437346443	1035	0	0
T97	14434	40	0	0
T99	10986	15	0	0
T100	3653	21	0	0
T101	2381	7	0	0
T102	12183	44	0	0
T103	2936	13	0	0
T104	2160	2	0	0
T105	2033	1	0	0
T106	7769	54	0	0
T142	3490	46	0	0