Group : i2c_env_pkg::i2c_interrupts_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : i2c_env_pkg::i2c_interrupts_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
i2c_env_pkg.interrupts_cg 100.00 1 100 1 64 64




Group Instance : i2c_env_pkg.interrupts_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance i2c_env_pkg.interrupts_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 45 0 45 100.00


Variables for Group Instance i2c_env_pkg.interrupts_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_acq_stretch 2 0 2 100.00 100 1 1 2
cp_acq_stretch_test 1 0 1 100.00 100 1 1 2
cp_acq_threshold 2 0 2 100.00 100 1 1 2
cp_acq_threshold_test 1 0 1 100.00 100 1 1 2
cp_cmd_complete 2 0 2 100.00 100 1 1 2
cp_cmd_complete_test 1 0 1 100.00 100 1 1 2
cp_fmt_threshold 2 0 2 100.00 100 1 1 2
cp_fmt_threshold_test 1 0 1 100.00 100 1 1 2
cp_host_timeout 2 0 2 100.00 100 1 1 2
cp_host_timeout_test 1 0 1 100.00 100 1 1 2
cp_nak 2 0 2 100.00 100 1 1 2
cp_nak_test 1 0 1 100.00 100 1 1 2
cp_rx_overflow 2 0 2 100.00 100 1 1 2
cp_rx_overflow_test 1 0 1 100.00 100 1 1 2
cp_rx_threshold 2 0 2 100.00 100 1 1 2
cp_rx_threshold_test 1 0 1 100.00 100 1 1 2
cp_scl_interference 2 0 2 100.00 100 1 1 2
cp_scl_interference_test 1 0 1 100.00 100 1 1 2
cp_sda_interference 2 0 2 100.00 100 1 1 2
cp_sda_interference_test 1 0 1 100.00 100 1 1 2
cp_sda_unstable 2 0 2 100.00 100 1 1 2
cp_sda_unstable_test 1 0 1 100.00 100 1 1 2
cp_stretch_timeout 2 0 2 100.00 100 1 1 2
cp_stretch_timeout_test 1 0 1 100.00 100 1 1 2
cp_tx_stretch 2 0 2 100.00 100 1 1 2
cp_tx_stretch_test 1 0 1 100.00 100 1 1 2
cp_tx_threshold 2 0 2 100.00 100 1 1 2
cp_tx_threshold_test 1 0 1 100.00 100 1 1 2
cp_unexp_stop 2 0 2 100.00 100 1 1 2
cp_unexp_stop_test 1 0 1 100.00 100 1 1 2


Summary for Variable cp_acq_stretch

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_acq_stretch

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 712987 1 T1 2548 T2 5576 T3 3
auto[1] 409 1 T2 7 T10 1 T51 1



Summary for Variable cp_acq_stretch_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for cp_acq_stretch_test

Excluded/Illegal bins
NAMECOUNTSTATUS
dis 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 134 1 T2 5 T18 1 T31 3



Summary for Variable cp_acq_threshold

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_acq_threshold

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 712688 1 T1 2548 T2 5577 T3 3
auto[1] 429 1 T2 26 T18 11 T265 1



Summary for Variable cp_acq_threshold_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for cp_acq_threshold_test

Excluded/Illegal bins
NAMECOUNTSTATUS
dis 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 154 1 T2 7 T18 3 T31 2



Summary for Variable cp_cmd_complete

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_cmd_complete

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 178293 1 T1 2546 T2 885 T3 3
auto[1] 535154 1 T1 2 T2 4716 T6 2771



Summary for Variable cp_cmd_complete_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for cp_cmd_complete_test

Excluded/Illegal bins
NAMECOUNTSTATUS
dis 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 149 1 T2 6 T18 1 T31 1



Summary for Variable cp_fmt_threshold

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_fmt_threshold

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 102509 1 T1 1892 T2 662 T3 1
auto[1] 606559 1 T1 656 T2 4939 T3 2



Summary for Variable cp_fmt_threshold_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for cp_fmt_threshold_test

Excluded/Illegal bins
NAMECOUNTSTATUS
dis 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 147 1 T2 4 T18 2 T31 2



Summary for Variable cp_host_timeout

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_host_timeout

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 713000 1 T1 2548 T2 5598 T3 3
auto[1] 307 1 T2 8 T110 5 T114 7



Summary for Variable cp_host_timeout_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for cp_host_timeout_test

Excluded/Illegal bins
NAMECOUNTSTATUS
dis 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 120 1 T2 4 T18 1 T31 1



Summary for Variable cp_nak

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_nak

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 713091 1 T1 2548 T2 5576 T3 3
auto[1] 351 1 T2 12 T20 1 T21 3



Summary for Variable cp_nak_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for cp_nak_test

Excluded/Illegal bins
NAMECOUNTSTATUS
dis 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 139 1 T2 8 T18 2 T31 1



Summary for Variable cp_rx_overflow

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_rx_overflow

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 712879 1 T1 2548 T2 5577 T3 3
auto[1] 410 1 T2 15 T31 12 T110 11



Summary for Variable cp_rx_overflow_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for cp_rx_overflow_test

Excluded/Illegal bins
NAMECOUNTSTATUS
dis 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 138 1 T2 5 T18 1 T31 3



Summary for Variable cp_rx_threshold

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_rx_threshold

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 712711 1 T1 2548 T2 5570 T3 3
auto[1] 490 1 T2 23 T6 1 T42 2



Summary for Variable cp_rx_threshold_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for cp_rx_threshold_test

Excluded/Illegal bins
NAMECOUNTSTATUS
dis 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 148 1 T2 8 T18 2 T31 1



Summary for Variable cp_scl_interference

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_scl_interference

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 708947 1 T1 2548 T2 5587 T3 3
auto[1] 378 1 T2 7 T31 7 T110 6



Summary for Variable cp_scl_interference_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for cp_scl_interference_test

Excluded/Illegal bins
NAMECOUNTSTATUS
dis 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 145 1 T2 5 T31 3 T110 4



Summary for Variable cp_sda_interference

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_sda_interference

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 708964 1 T1 2548 T2 5576 T3 3
auto[1] 408 1 T2 20 T18 5 T110 4



Summary for Variable cp_sda_interference_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for cp_sda_interference_test

Excluded/Illegal bins
NAMECOUNTSTATUS
dis 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 146 1 T2 7 T18 3 T31 2



Summary for Variable cp_sda_unstable

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_sda_unstable

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 708993 1 T1 2548 T2 5603 T3 3
auto[1] 395 1 T2 15 T18 11 T31 5



Summary for Variable cp_sda_unstable_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for cp_sda_unstable_test

Excluded/Illegal bins
NAMECOUNTSTATUS
dis 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 139 1 T2 5 T18 2 T31 1



Summary for Variable cp_stretch_timeout

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_stretch_timeout

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 682087 1 T1 2543 T2 5258 T3 3
auto[1] 27288 1 T1 5 T2 346 T6 94



Summary for Variable cp_stretch_timeout_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for cp_stretch_timeout_test

Excluded/Illegal bins
NAMECOUNTSTATUS
dis 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 140 1 T2 7 T18 1 T31 1



Summary for Variable cp_tx_stretch

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_tx_stretch

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 712990 1 T1 2548 T2 5596 T3 3
auto[1] 406 1 T2 2 T114 24 T267 9



Summary for Variable cp_tx_stretch_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for cp_tx_stretch_test

Excluded/Illegal bins
NAMECOUNTSTATUS
dis 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 145 1 T2 2 T18 1 T110 2



Summary for Variable cp_tx_threshold

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_tx_threshold

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4742 1 T1 3 T2 43 T3 1
auto[1] 704225 1 T1 2545 T2 5564 T3 2



Summary for Variable cp_tx_threshold_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for cp_tx_threshold_test

Excluded/Illegal bins
NAMECOUNTSTATUS
dis 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 149 1 T2 5 T18 3 T31 1



Summary for Variable cp_unexp_stop

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_unexp_stop

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 713141 1 T1 2548 T2 5598 T3 3
auto[1] 376 1 T2 13 T18 7 T31 4



Summary for Variable cp_unexp_stop_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for cp_unexp_stop_test

Excluded/Illegal bins
NAMECOUNTSTATUS
dis 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 146 1 T2 6 T18 1 T31 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%