SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
i2c_env_pkg.b2b_txn_host_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
i2c_env_pkg.b2b_txn_target_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 8 | 0 | 8 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
B2B_txn_cp | 8 | 0 | 8 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 8 | 0 | 8 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
B2B_txn_cp | 8 | 0 | 8 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 8 | 0 | 8 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
b2b_read_different_addr | 2028 | 1 | T1 | 1 | T6 | 5 | T32 | 9 | ||||
b2b_read_same_addr | 323 | 1 | T19 | 1 | T20 | 3 | T39 | 8 | ||||
write_after_read_different_addr | 2064 | 1 | T1 | 1 | T6 | 4 | T32 | 6 | ||||
write_after_read_same_addr | 35 | 1 | T6 | 1 | T204 | 1 | T273 | 1 | ||||
read_after_write_different_addr | 2058 | 1 | T6 | 5 | T32 | 7 | T29 | 6 | ||||
read_after_write_same_addr | 37 | 1 | T33 | 1 | T153 | 1 | T183 | 1 | ||||
b2b_write_different_addr | 2065 | 1 | T1 | 1 | T6 | 6 | T32 | 14 | ||||
b2b_write_same_addr | 341 | 1 | T32 | 1 | T42 | 1 | T19 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 8 | 0 | 8 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
b2b_read_different_addr | 5370 | 1 | T3 | 6 | T4 | 46 | T8 | 36 | ||||
b2b_read_same_addr | 13958 | 1 | T3 | 9 | T4 | 61 | T8 | 20 | ||||
write_after_read_different_addr | 5761 | 1 | T3 | 9 | T66 | 20 | T67 | 16 | ||||
write_after_read_same_addr | 66 | 1 | T274 | 17 | T275 | 7 | T276 | 13 | ||||
read_after_write_different_addr | 5741 | 1 | T3 | 9 | T66 | 20 | T67 | 16 | ||||
read_after_write_same_addr | 67 | 1 | T274 | 17 | T275 | 7 | T276 | 14 | ||||
b2b_write_different_addr | 5100 | 1 | T5 | 17 | T51 | 30 | T57 | 1 | ||||
b2b_write_same_addr | 12789 | 1 | T3 | 5 | T5 | 23 | T66 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |