Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.48	100.00	100.00	93.91			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	405160665	0	0	0
ctrl_rd_A	405160665	3307	0	0
host_fifo_config_rd_A	405160665	5288	0	0
host_nack_handler_timeout_rd_A	405160665	1610	0	0
host_timeout_ctrl_rd_A	405160665	1403	0	0
intr_enable_rd_A	405160665	5242	0	0
ovrd_rd_A	405160665	2797	0	0
target_fifo_config_rd_A	405160665	1652	0	0
target_id_rd_A	405160665	2420	0	0
target_timeout_ctrl_rd_A	405160665	1794	0	0
timeout_ctrl_rd_A	405160665	2000	0	0
timing0_rd_A	405160665	1769	0	0
timing1_rd_A	405160665	1796	0	0
timing2_rd_A	405160665	1713	0	0
timing3_rd_A	405160665	1858	0	0
timing4_rd_A	405160665	1714	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405160665	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405160665	3307	0	0
T96	13897	258	0	0
T97	2135	31	0	0
T98	5799	114	0	0
T99	2242	28	0	0
T100	2759	37	0	0
T101	2336	37	0	0
T102	3920	46	0	0
T103	5916	3	0	0
T104	6895	95	0	0
T105	17783	69	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405160665	5288	0	0
T29	319055	163	0	0
T32	506448	243	0	0
T45	82484	0	0	0
T51	50167	0	0	0
T54	4959	0	0	0
T57	275099	0	0	0
T66	89365	0	0	0
T67	67804	0	0	0
T68	88051	0	0	0
T89	2859	0	0	0
T106	0	128	0	0
T107	0	124	0	0
T108	0	231	0	0
T109	0	168	0	0
T110	0	347	0	0
T111	0	210	0	0
T112	0	209	0	0
T113	0	139	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405160665	1610	0	0
T96	13897	102	0	0
T97	2135	8	0	0
T98	5799	91	0	0
T99	2242	11	0	0
T100	2759	7	0	0
T101	2336	15	0	0
T102	3920	24	0	0
T103	5916	5	0	0
T104	6895	47	0	0
T105	17783	13	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405160665	1403	0	0
T96	13897	77	0	0
T97	2135	2	0	0
T98	5799	89	0	0
T99	2242	2	0	0
T100	2759	8	0	0
T101	2336	3	0	0
T102	3920	17	0	0
T103	5916	12	0	0
T104	6895	20	0	0
T105	17783	22	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405160665	5242	0	0
T23	0	15	0	0
T96	0	568	0	0
T97	0	8	0	0
T110	277026	22	0	0
T114	0	39	0	0
T115	0	20	0	0
T116	0	11	0	0
T117	0	14	0	0
T118	0	7	0	0
T119	0	12	0	0
T120	72833	0	0	0
T121	941558	0	0	0
T122	322378	0	0	0
T123	51459	0	0	0
T124	78286	0	0	0
T125	129204	0	0	0
T126	60916	0	0	0
T127	40451	0	0	0
T128	49586	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405160665	2797	0	0
T29	319055	0	0	0
T45	82484	0	0	0
T51	50167	0	0	0
T54	4959	0	0	0
T57	275099	0	0	0
T61	66170	0	0	0
T67	67804	0	0	0
T68	88051	0	0	0
T71	0	9	0	0
T89	2859	61	0	0
T129	0	37	0	0
T130	0	77	0	0
T131	0	55	0	0
T132	0	47	0	0
T133	0	59	0	0
T134	0	66	0	0
T135	0	50	0	0
T136	0	57	0	0
T137	29748	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405160665	1652	0	0
T96	13897	88	0	0
T97	2135	8	0	0
T98	5799	101	0	0
T99	2242	14	0	0
T100	2759	16	0	0
T101	2336	16	0	0
T102	3920	14	0	0
T103	5916	22	0	0
T104	6895	41	0	0
T105	17783	49	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405160665	2420	0	0
T96	13897	154	0	0
T97	2135	11	0	0
T98	5799	102	0	0
T99	2242	28	0	0
T100	2759	9	0	0
T101	2336	10	0	0
T102	3920	40	0	0
T103	5916	9	0	0
T104	6895	65	0	0
T105	17783	47	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405160665	1794	0	0
T96	13897	116	0	0
T97	2135	3	0	0
T98	5799	114	0	0
T99	2242	9	0	0
T100	2759	10	0	0
T101	2336	13	0	0
T102	3920	15	0	0
T104	6895	60	0	0
T105	17783	43	0	0
T138	5956	34	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405160665	2000	0	0
T96	13897	178	0	0
T97	2135	16	0	0
T98	5799	115	0	0
T100	2759	17	0	0
T101	2336	8	0	0
T102	3920	10	0	0
T103	5916	8	0	0
T104	6895	54	0	0
T105	17783	32	0	0
T138	5956	45	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405160665	1769	0	0
T96	13897	95	0	0
T97	2135	3	0	0
T98	5799	94	0	0
T99	2242	10	0	0
T100	2759	6	0	0
T101	2336	4	0	0
T102	3920	27	0	0
T103	5916	7	0	0
T104	6895	21	0	0
T105	17783	39	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405160665	1796	0	0
T96	13897	120	0	0
T97	2135	11	0	0
T98	5799	92	0	0
T99	2242	5	0	0
T100	2759	13	0	0
T101	2336	16	0	0
T102	3920	24	0	0
T103	5916	20	0	0
T104	6895	24	0	0
T105	17783	35	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405160665	1713	0	0
T96	13897	128	0	0
T97	2135	7	0	0
T98	5799	115	0	0
T99	2242	3	0	0
T100	2759	9	0	0
T101	2336	14	0	0
T102	3920	16	0	0
T103	5916	10	0	0
T104	6895	35	0	0
T105	17783	18	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405160665	1858	0	0
T96	13897	132	0	0
T97	2135	7	0	0
T98	5799	103	0	0
T99	2242	13	0	0
T100	2759	15	0	0
T101	2336	20	0	0
T102	3920	36	0	0
T103	5916	45	0	0
T104	6895	33	0	0
T105	17783	85	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405160665	1714	0	0
T96	13897	92	0	0
T97	2135	3	0	0
T98	5799	96	0	0
T99	2242	11	0	0
T100	2759	19	0	0
T101	2336	21	0	0
T102	3920	14	0	0
T103	5916	5	0	0
T104	6895	22	0	0
T105	17783	22	0	0