Unified Coverage Report :: Module :: prim_generic_flop_2sync

Module : prim_generic_flop_2sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_2sync_0/rtl/prim_generic_flop_2sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_core.u_i2c_sync_scl.gen_generic.u_impl_generic
tb.dut.i2c_core.u_i2c_sync_sda.gen_generic.u_impl_generic

---

Module Instance : tb.dut.i2c_core.u_i2c_sync_scl.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_i2c_sync_scl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_sync_1	100.00	100.00				100.00
u_sync_2	100.00	100.00				100.00

---

Module Instance : tb.dut.i2c_core.u_i2c_sync_sda.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_i2c_sync_sda

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_sync_1	100.00	100.00				100.00
u_sync_2	100.00	100.00				100.00