SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
i2c_env_pkg.status_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 20 | 0 | 20 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_acqempty | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_acqfull | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_fmtempty | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_fmtfull | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_hostidle | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_rxempty | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_rxfull | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_targetidle | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_txempty | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_txfull | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 1154274 | 1 | T1 | 2 | T2 | 546 | T3 | 839 | ||||
auto[1] | 32703045 | 1 | T1 | 21 | T2 | 94 | T3 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 33835155 | 1 | T1 | 23 | T2 | 640 | T3 | 283 | ||||
auto[1] | 22164 | 1 | T3 | 558 | T52 | 6 | T64 | 628 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 31821858 | 1 | T8 | 11705 | T9 | 47 | T14 | 2101 | ||||
auto[1] | 2035461 | 1 | T1 | 23 | T2 | 640 | T3 | 841 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 27014827 | 1 | T1 | 23 | T2 | 640 | T3 | 841 | ||||
auto[1] | 6842492 | 1 | T14 | 360 | T17 | 119564 | T24 | 48402 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 31818912 | 1 | T8 | 11705 | T9 | 58 | T14 | 2101 | ||||
auto[1] | 2038407 | 1 | T1 | 23 | T2 | 640 | T3 | 841 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 6895056 | 1 | T8 | 367 | T15 | 1386 | T16 | 287 | ||||
auto[1] | 26962263 | 1 | T1 | 23 | T2 | 640 | T3 | 841 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 33803567 | 1 | T1 | 23 | T2 | 640 | T3 | 841 | ||||
auto[1] | 53752 | 1 | T15 | 1 | T40 | 442 | T17 | 81 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 1715996 | 1 | T1 | 2 | T2 | 638 | T3 | 572 | ||||
auto[1] | 32141323 | 1 | T1 | 21 | T2 | 2 | T3 | 269 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 1584296 | 1 | T1 | 22 | T4 | 59 | T5 | 266 | ||||
auto[1] | 32273023 | 1 | T1 | 1 | T2 | 640 | T3 | 841 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 33857313 | 1 | T1 | 23 | T2 | 640 | T3 | 841 | ||||
auto[1] | 6 | 1 | T178 | 1 | T291 | 1 | T292 | 1 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |