Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	29722964	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

7808327

1

T1

22

T2

499

T3

445

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	36714118	1			T1	33		T2	1125		T3	1683
values[0x0]	408152	1			T1	21		T2	123		T3	9
values[0x1]	409021	1			T1	17		T2	112		T3	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	20738156	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

16793135

1

T1

30

T2

716

T3

736

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	155345	1			T5	8		T8	91		T10	3
valid_sources[0x01]	148056	1			T5	5		T8	90		T10	2
valid_sources[0x02]	154256	1			T5	6		T8	90		T9	1
valid_sources[0x03]	130003	1			T5	8		T8	76		T10	1
valid_sources[0x04]	166409	1			T5	1		T8	95		T14	2
valid_sources[0x05]	156832	1			T5	6		T8	88		T14	4
valid_sources[0x06]	151023	1			T5	2		T8	106		T10	1
valid_sources[0x07]	141224	1			T5	2		T8	92		T10	4
valid_sources[0x08]	129512	1			T5	5		T8	88		T10	1
valid_sources[0x09]	139138	1			T5	3		T8	77		T10	4
valid_sources[0x0a]	133847	1			T5	6		T8	88		T10	1
valid_sources[0x0b]	137592	1			T5	7		T8	80		T14	2
valid_sources[0x0c]	130971	1			T5	8		T8	83		T9	1
valid_sources[0x0d]	140286	1			T5	3		T6	114		T8	108
valid_sources[0x0e]	143560	1			T5	11		T8	81		T14	9
valid_sources[0x0f]	139839	1			T5	6		T8	112		T10	1
valid_sources[0x10]	143211	1			T1	4		T5	3		T8	115
valid_sources[0x11]	149285	1			T5	5		T8	72		T10	2
valid_sources[0x12]	169253	1			T5	6		T8	109		T10	2
valid_sources[0x13]	145897	1			T5	3		T8	103		T10	1
valid_sources[0x14]	138241	1			T5	4		T8	112		T10	1
valid_sources[0x15]	145670	1			T5	5		T8	105		T10	1
valid_sources[0x16]	145855	1			T3	1698		T5	8		T8	78
valid_sources[0x17]	146089	1			T5	3		T8	88		T10	3
valid_sources[0x18]	155395	1			T5	14		T8	83		T10	1
valid_sources[0x19]	137336	1			T5	2		T8	87		T10	1
valid_sources[0x1a]	135107	1			T5	2		T8	74		T14	6
valid_sources[0x1b]	139785	1			T5	4		T8	109		T14	12
valid_sources[0x1c]	162070	1			T5	1		T8	117		T14	13
valid_sources[0x1d]	145965	1			T5	6		T8	87		T10	2
valid_sources[0x1e]	162155	1			T5	3		T8	95		T14	13
valid_sources[0x1f]	155901	1			T5	6		T8	108		T10	1
valid_sources[0x20]	137727	1			T5	3		T8	111		T10	1
valid_sources[0x21]	138027	1			T5	7		T8	94		T10	1
valid_sources[0x22]	165940	1			T5	6		T8	72		T10	2
valid_sources[0x23]	149397	1			T5	9		T8	114		T14	10
valid_sources[0x24]	148507	1			T5	4		T8	102		T14	7
valid_sources[0x25]	161541	1			T5	7		T8	122		T10	1
valid_sources[0x26]	153343	1			T5	2		T8	104		T10	1
valid_sources[0x27]	145069	1			T5	1		T8	111		T9	8
valid_sources[0x28]	149822	1			T5	2		T8	103		T10	1
valid_sources[0x29]	150546	1			T5	6		T8	108		T9	8
valid_sources[0x2a]	143004	1			T1	8		T5	5		T8	101
valid_sources[0x2b]	153668	1			T5	1		T8	75		T14	10
valid_sources[0x2c]	137981	1			T5	3		T8	89		T10	1
valid_sources[0x2d]	146953	1			T5	7		T8	98		T10	2
valid_sources[0x2e]	137222	1			T5	8		T8	97		T14	6
valid_sources[0x2f]	152328	1			T5	2		T8	103		T14	11
valid_sources[0x30]	150661	1			T5	6		T8	72		T9	4
valid_sources[0x31]	146239	1			T5	9		T8	71		T14	8
valid_sources[0x32]	129143	1			T5	4		T8	92		T14	4
valid_sources[0x33]	141125	1			T5	9		T8	86		T14	13
valid_sources[0x34]	141604	1			T5	4		T8	92		T9	6
valid_sources[0x35]	147474	1			T5	5		T8	86		T14	8
valid_sources[0x36]	165015	1			T5	2		T8	95		T10	2
valid_sources[0x37]	141030	1			T5	9		T8	106		T14	8
valid_sources[0x38]	131705	1			T5	3		T8	88		T14	14
valid_sources[0x39]	161972	1			T5	8		T8	68		T14	9
valid_sources[0x3a]	144797	1			T5	6		T8	86		T10	2
valid_sources[0x3b]	158439	1			T5	6		T8	105		T14	5
valid_sources[0x3c]	142440	1			T5	3		T8	95		T14	7
valid_sources[0x3d]	130616	1			T5	10		T8	98		T10	1
valid_sources[0x3e]	170381	1			T5	5		T8	95		T14	4
valid_sources[0x3f]	151994	1			T5	6		T8	79		T10	2
valid_sources[0x40]	147564	1			T5	7		T8	109		T14	10
valid_sources[0x41]	141274	1			T5	8		T8	93		T14	5
valid_sources[0x42]	129117	1			T2	1360		T5	2		T8	108
valid_sources[0x43]	138961	1			T5	9		T8	89		T9	3
valid_sources[0x44]	141203	1			T5	9		T8	79		T10	1
valid_sources[0x45]	142674	1			T5	6		T8	103		T10	1
valid_sources[0x46]	158788	1			T5	2		T8	97		T10	2
valid_sources[0x47]	144449	1			T5	10		T8	113		T10	1
valid_sources[0x48]	137057	1			T5	7		T8	97		T10	2
valid_sources[0x49]	144573	1			T1	7		T5	3		T8	91
valid_sources[0x4a]	146943	1			T5	3		T8	105		T10	3
valid_sources[0x4b]	162444	1			T5	10		T8	112		T10	1
valid_sources[0x4c]	149772	1			T5	9		T8	125		T14	13
valid_sources[0x4d]	148121	1			T5	6		T8	106		T14	14
valid_sources[0x4e]	143332	1			T1	6		T5	2		T8	101
valid_sources[0x4f]	151954	1			T5	6		T8	81		T9	4
valid_sources[0x50]	137756	1			T5	1		T8	117		T9	6
valid_sources[0x51]	143088	1			T5	3		T8	88		T10	1
valid_sources[0x52]	151457	1			T5	5		T8	99		T14	16
valid_sources[0x53]	139193	1			T5	3		T8	86		T14	10
valid_sources[0x54]	128954	1			T5	8		T8	82		T10	1
valid_sources[0x55]	144618	1			T5	3		T8	103		T14	5
valid_sources[0x56]	155945	1			T5	14		T8	100		T10	2
valid_sources[0x57]	138115	1			T1	2		T5	8		T8	94
valid_sources[0x58]	145631	1			T5	3		T8	99		T10	3
valid_sources[0x59]	139837	1			T5	5		T8	105		T14	13
valid_sources[0x5a]	152025	1			T5	5		T8	98		T10	2
valid_sources[0x5b]	130100	1			T5	11		T8	90		T10	1
valid_sources[0x5c]	156341	1			T8	92		T9	1		T10	1
valid_sources[0x5d]	149935	1			T5	2		T8	56		T10	2
valid_sources[0x5e]	144148	1			T5	4		T8	70		T10	3
valid_sources[0x5f]	141530	1			T1	6		T5	8		T8	114
valid_sources[0x60]	141617	1			T5	3		T8	89		T10	1
valid_sources[0x61]	140312	1			T5	2		T8	86		T9	1
valid_sources[0x62]	131138	1			T5	8		T8	59		T10	3
valid_sources[0x63]	146555	1			T1	6		T5	6		T8	74
valid_sources[0x64]	142034	1			T5	6		T8	99		T10	3
valid_sources[0x65]	144695	1			T5	7		T8	74		T9	4
valid_sources[0x66]	130513	1			T5	3		T8	77		T14	8
valid_sources[0x67]	135860	1			T5	10		T8	118		T10	1
valid_sources[0x68]	146920	1			T5	7		T8	100		T14	17
valid_sources[0x69]	131256	1			T5	5		T8	112		T14	10
valid_sources[0x6a]	134127	1			T5	4		T8	82		T14	9
valid_sources[0x6b]	140335	1			T8	96		T9	3		T14	10
valid_sources[0x6c]	141276	1			T5	3		T8	103		T10	3
valid_sources[0x6d]	169527	1			T1	14		T5	7		T8	104
valid_sources[0x6e]	166847	1			T5	5		T8	88		T9	1
valid_sources[0x6f]	141633	1			T5	5		T8	94		T10	3
valid_sources[0x70]	155268	1			T5	5		T8	109		T10	4
valid_sources[0x71]	138499	1			T8	103		T10	3		T14	9
valid_sources[0x72]	138796	1			T5	7		T8	115		T10	3
valid_sources[0x73]	158056	1			T5	9		T8	93		T9	1
valid_sources[0x74]	146072	1			T5	2		T8	90		T14	14
valid_sources[0x75]	136851	1			T5	2		T8	100		T14	5
valid_sources[0x76]	141112	1			T5	4		T8	90		T10	1
valid_sources[0x77]	154416	1			T5	2		T8	109		T14	4
valid_sources[0x78]	132653	1			T5	5		T8	90		T10	3
valid_sources[0x79]	148697	1			T5	8		T8	98		T10	2
valid_sources[0x7a]	138665	1			T5	3		T8	120		T10	1
valid_sources[0x7b]	137501	1			T1	2		T5	12		T8	98
valid_sources[0x7c]	146419	1			T5	5		T8	87		T14	14
valid_sources[0x7d]	161136	1			T5	5		T8	85		T10	3
valid_sources[0x7e]	157633	1			T5	5		T8	104		T10	2
valid_sources[0x7f]	138724	1			T5	3		T8	100		T9	3
valid_sources[0x80]	143347	1			T5	1		T8	94		T10	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7444865

1

T1

5

T2

315

T3

431

values[0x0]

all_enables

biggest_size

215636

1

T1

11

T2

99

T3

9

values[0x1]

all_enables

biggest_size

147826

1

T1

6

T2

85

T3

5