Summary for Variable cp_abyte
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
5 |
0 |
5 |
100.00 |
User Defined Bins for cp_abyte
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_ones |
1160 |
1 |
|
|
T2 |
1 |
|
T3 |
4 |
|
T5 |
2 |
high |
61872 |
1 |
|
|
T1 |
1 |
|
T2 |
168 |
|
T3 |
158 |
med |
114517 |
1 |
|
|
T2 |
170 |
|
T3 |
380 |
|
T4 |
6 |
sml |
114117 |
1 |
|
|
T1 |
3 |
|
T2 |
140 |
|
T3 |
290 |
all_zero |
1354 |
1 |
|
|
T2 |
2 |
|
T3 |
7 |
|
T5 |
2 |
Summary for Variable cp_action
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for cp_action
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
rstart |
33002 |
1 |
|
|
T1 |
2 |
|
T2 |
101 |
|
T3 |
76 |
start |
12844 |
1 |
|
|
T1 |
1 |
|
T2 |
3 |
|
T3 |
5 |
stop |
12888 |
1 |
|
|
T1 |
1 |
|
T2 |
3 |
|
T3 |
5 |
none |
234286 |
1 |
|
|
T2 |
374 |
|
T3 |
753 |
|
T5 |
234 |
Summary for Variable cp_request_type
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_request_type
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
write |
6653 |
1 |
|
|
T2 |
3 |
|
T3 |
5 |
|
T5 |
5 |
read |
6191 |
1 |
|
|
T1 |
1 |
|
T4 |
1 |
|
T5 |
10 |
Summary for Variable cp_target_read_ack_nack
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
0 |
0 |
0 |
|
User Defined Bins for cp_target_read_ack_nack
Excluded/Illegal bins
NAME | COUNT | STATUS |
read_req_nack_before_rstart |
0 |
Excluded |
read_req_ack_before_stop |
0 |
Excluded |
read_req_nack_before_stop |
0 |
Excluded |
read_req_ack_before_rstart |
0 |
Excluded |
Summary for Cross cp_abyte_X_cp_action
Samples crossed: cp_abyte cp_action
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
13 |
1 |
12 |
92.31 |
1 |
Automatically Generated Cross Bins |
10 |
1 |
9 |
90.00 |
1 |
User Defined Cross Bins |
3 |
0 |
3 |
100.00 |
|
Automatically Generated Cross Bins for cp_abyte_X_cp_action
Uncovered bins
cp_abyte | cp_action | COUNT | AT LEAST | NUMBER | STATUS |
[all_ones] |
[stop] |
0 |
1 |
1 |
|
Covered bins
cp_abyte | cp_action | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_ones |
rstart |
152 |
1 |
|
|
T274 |
13 |
|
T275 |
11 |
|
T276 |
4 |
high |
rstart |
6846 |
1 |
|
|
T2 |
81 |
|
T62 |
3 |
|
T167 |
26 |
high |
stop |
2815 |
1 |
|
|
T1 |
1 |
|
T5 |
2 |
|
T64 |
29 |
med |
rstart |
13571 |
1 |
|
|
T2 |
20 |
|
T3 |
76 |
|
T4 |
5 |
med |
stop |
4919 |
1 |
|
|
T3 |
2 |
|
T4 |
1 |
|
T5 |
6 |
sml |
rstart |
12253 |
1 |
|
|
T1 |
2 |
|
T4 |
1 |
|
T6 |
1 |
sml |
stop |
5050 |
1 |
|
|
T2 |
3 |
|
T3 |
3 |
|
T5 |
7 |
all_zero |
rstart |
180 |
1 |
|
|
T277 |
12 |
|
T276 |
29 |
|
T278 |
14 |
all_zero |
stop |
104 |
1 |
|
|
T52 |
1 |
|
T78 |
1 |
|
T65 |
2 |
User Defined Cross Bins for cp_abyte_X_cp_action
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
write_address_byte |
12844 |
1 |
|
|
T1 |
1 |
|
T2 |
3 |
|
T3 |
5 |
read_address_byte |
12844 |
1 |
|
|
T1 |
1 |
|
T2 |
3 |
|
T3 |
5 |
data_byte |
234286 |
1 |
|
|
T2 |
374 |
|
T3 |
753 |
|
T5 |
234 |