Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_fifo_sync_cnt
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.u_fifo_cnt 88.21 100.00 80.00 84.62
tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.u_fifo_cnt 94.10 100.00 90.00 92.31
tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.u_fifo_cnt 94.10 100.00 90.00 92.31
tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.u_fifo_cnt 94.10 100.00 90.00 92.31
tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00 100.00
tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_sram_ptrs 100.00 100.00 100.00 100.00
tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00 100.00
tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_sram_ptrs 100.00 100.00 100.00 100.00
tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00 100.00
tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_sram_ptrs 100.00 100.00 100.00 100.00
tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00 100.00
tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_sram_ptrs 100.00 100.00 100.00 100.00


Module Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.u_fifo_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
88.21 100.00 80.00 84.62


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
88.21 100.00 80.00 84.62


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
91.67 100.00 66.67 100.00 100.00 u_inp_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.u_fifo_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.10 100.00 90.00 92.31


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.10 100.00 90.00 92.31


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.75 100.00 75.00 100.00 100.00 u_inp_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.u_fifo_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.10 100.00 90.00 92.31


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.10 100.00 90.00 92.31


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.75 100.00 75.00 100.00 100.00 u_inp_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.u_fifo_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.10 100.00 90.00 92.31


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.10 100.00 90.00 92.31


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.75 100.00 75.00 100.00 100.00 u_inp_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.u_fifo_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.79 100.00 79.17 100.00 100.00 u_oup_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_sram_ptrs

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.63 100.00 74.51 100.00 100.00 u_fmt_fifo_sram_adapter


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.u_fifo_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.79 100.00 79.17 100.00 100.00 u_oup_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_sram_ptrs

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.12 100.00 76.47 100.00 100.00 u_rx_fifo_sram_adapter


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.u_fifo_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.79 100.00 79.17 100.00 100.00 u_oup_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_sram_ptrs

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.63 100.00 74.51 100.00 100.00 u_tx_fifo_sram_adapter


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.u_fifo_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.83 100.00 83.33 100.00 100.00 u_oup_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_sram_ptrs

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.59 100.00 82.35 100.00 100.00 u_acq_fifo_sram_adapter


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=2,Secure=0,PtrW=1,DepthW=2,WrapPtrW=2 )
Line Coverage for Module self-instances :
SCORELINE
94.10 100.00
tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.u_fifo_cnt

SCORELINE
100.00 100.00
tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.u_fifo_cnt

SCORELINE
88.21 100.00
tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.u_fifo_cnt

SCORELINE
100.00 100.00
tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.u_fifo_cnt

SCORELINE
94.10 100.00
tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.u_fifo_cnt

SCORELINE
100.00 100.00
tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.u_fifo_cnt

SCORELINE
94.10 100.00
tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.u_fifo_cnt

SCORELINE
100.00 100.00
tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.u_fifo_cnt

Line No.TotalCoveredPercent
TOTAL2727100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6811100.00
ALWAYS11388100.00
ALWAYS12588100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
41 1 1
42 1 1
46 1 1
47 1 1
51 1 1
52 1 1
55 1 1
56 1 1
59 1 1
61 1 1
68 1 1
113 1 1
114 1 1
115 1 1
116 1 1
117 1 1
118 1 1
119 1 1
120 1 1
MISSING_ELSE
125 1 1
126 1 1
127 1 1
128 1 1
129 1 1
130 1 1
131 1 1
132 1 1
MISSING_ELSE

Line Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=62,Secure=0,PtrW=6,DepthW=6,WrapPtrW=7 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_sram_ptrs

SCORELINE
100.00 100.00
tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_sram_ptrs

SCORELINE
100.00 100.00
tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_sram_ptrs

Line No.TotalCoveredPercent
TOTAL2727100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6811100.00
ALWAYS11388100.00
ALWAYS12588100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
41 1 1
42 1 1
46 1 1
47 1 1
51 1 1
52 1 1
55 1 1
56 1 1
59 1 1
61 1 1
68 1 1
113 1 1
114 1 1
115 1 1
116 1 1
117 1 1
118 1 1
119 1 1
120 1 1
MISSING_ELSE
125 1 1
126 1 1
127 1 1
128 1 1
129 1 1
130 1 1
131 1 1
132 1 1
MISSING_ELSE

Line Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=266,Secure=0,PtrW=9,DepthW=9,WrapPtrW=10 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_sram_ptrs

Line No.TotalCoveredPercent
TOTAL2727100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6811100.00
ALWAYS11388100.00
ALWAYS12588100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
41 1 1
42 1 1
46 1 1
47 1 1
51 1 1
52 1 1
55 1 1
56 1 1
59 1 1
61 1 1
68 1 1
113 1 1
114 1 1
115 1 1
116 1 1
117 1 1
118 1 1
119 1 1
120 1 1
MISSING_ELSE
125 1 1
126 1 1
127 1 1
128 1 1
129 1 1
130 1 1
131 1 1
132 1 1
MISSING_ELSE

Cond Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=266,Secure=0,PtrW=9,DepthW=9,WrapPtrW=10 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_sram_ptrs

TotalCoveredPercent
Conditions2020100.00
Logical2020100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 9'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT2,T3,T10
10CoveredT2,T3,T5
11CoveredT2,T3,T10 

 LINE       51
 SUB-EXPRESSION (wptr_o == 9'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T10 

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 9'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT2,T3,T10
10CoveredT2,T3,T5
11CoveredT2,T3,T10 

 LINE       52
 SUB-EXPRESSION (rptr_o == 9'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T10 

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT10,T54,T60 

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       68
 EXPRESSION (full_o ? (9'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((9'(wptr_o) - 9'(rptr_o))) : (((9'(Depth) - 9'(rptr_o)) + 9'(wptr_o)))))
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT10,T54,T60 

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((9'(wptr_o) - 9'(rptr_o))) : (((9'(Depth) - 9'(rptr_o)) + 9'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0CoveredT2,T3,T10
1CoveredT1,T2,T3 

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0CoveredT2,T3,T10
1CoveredT1,T2,T3
Cond Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=2,Secure=0,PtrW=1,DepthW=2,WrapPtrW=2 )
Cond Coverage for Module self-instances :
SCORECOND
94.10 90.00
tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.u_fifo_cnt

SCORECOND
100.00 100.00
tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.u_fifo_cnt

SCORECOND
88.21 80.00
tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.u_fifo_cnt

SCORECOND
100.00 100.00
tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.u_fifo_cnt

SCORECOND
94.10 90.00
tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.u_fifo_cnt

SCORECOND
100.00 100.00
tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.u_fifo_cnt

SCORECOND
94.10 90.00
tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.u_fifo_cnt

SCORECOND
100.00 100.00
tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.u_fifo_cnt

TotalCoveredPercent
Conditions2020100.00
Logical2020100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT1,T4,T5
10CoveredT1,T4,T5
11CoveredT1,T4,T5 

 LINE       51
 SUB-EXPRESSION (wptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5 

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT1,T4,T5
10CoveredT1,T4,T5
11CoveredT1,T4,T5 

 LINE       52
 SUB-EXPRESSION (rptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5 

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5 

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       68
 EXPRESSION (full_o ? (2'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o)))))
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5 

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0CoveredT8,T14,T15
1CoveredT1,T2,T3 

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0CoveredT8,T14,T15
1CoveredT1,T2,T3
Cond Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=62,Secure=0,PtrW=6,DepthW=6,WrapPtrW=7 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_sram_ptrs

SCORECOND
100.00 100.00
tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_sram_ptrs

SCORECOND
100.00 100.00
tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_sram_ptrs

TotalCoveredPercent
Conditions2020100.00
Logical2020100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 6'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT5,T8,T14
10CoveredT1,T4,T8
11CoveredT5,T8,T14 

 LINE       51
 SUB-EXPRESSION (wptr_o == 6'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T8,T14 

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 6'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT5,T8,T14
10CoveredT1,T4,T8
11CoveredT5,T8,T14 

 LINE       52
 SUB-EXPRESSION (rptr_o == 6'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T8,T14 

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT14,T15,T40 

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       68
 EXPRESSION (full_o ? (6'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((6'(wptr_o) - 6'(rptr_o))) : (((6'(Depth) - 6'(rptr_o)) + 6'(wptr_o)))))
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT14,T15,T40 

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((6'(wptr_o) - 6'(rptr_o))) : (((6'(Depth) - 6'(rptr_o)) + 6'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0CoveredT5,T8,T14
1CoveredT1,T2,T3 

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0CoveredT5,T8,T14
1CoveredT1,T2,T3
Branch Coverage for Module : prim_fifo_sync_cnt
Line No.TotalCoveredPercent
Branches 13 13 100.00
TERNARY 68 3 3 100.00
IF 113 5 5 100.00
IF 125 5 5 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	68	(full_o) ? 
-2-:	68	((wptr_wrap_msb == rptr_wrap_msb)) ?

Branches:
-1--2-StatusTests
1 - Covered T8,T9,T14
0 1 Covered T1,T2,T3
0 0 Covered T8,T14,T15 



	LineNo.	Expression
-1-:	113	if ((!rst_ni))
-2-:	115	if (clr_i)
-3-:	117	if (wptr_wrap_set)
-4-:	119	if (incr_wptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T8,T9,T14
0 0 0 1 Covered T1,T8,T9
0 0 0 0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	125	if ((!rst_ni))
-2-:	127	if (clr_i)
-3-:	129	if (rptr_wrap_set)
-4-:	131	if (incr_rptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T8,T9,T14
0 0 0 1 Covered T8,T9,T14
0 0 0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
TOTAL2727100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6811100.00
ALWAYS11388100.00
ALWAYS12588100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
41 1 1
42 1 1
46 1 1
47 1 1
51 1 1
52 1 1
55 1 1
56 1 1
59 1 1
61 1 1
68 1 1
113 1 1
114 1 1
115 1 1
116 1 1
117 1 1
118 1 1
119 1 1
120 1 1
MISSING_ELSE
125 1 1
126 1 1
127 1 1
128 1 1
129 1 1
130 1 1
131 1 1
132 1 1
MISSING_ELSE

Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.u_fifo_cnt
TotalCoveredPercent
Conditions201680.00
Logical201680.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT8,T15,T16
10CoveredT8,T15,T16
11CoveredT8,T15,T16 

 LINE       51
 SUB-EXPRESSION (wptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT8,T15,T16 

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT8,T15,T16
10CoveredT8,T15,T16
11CoveredT8,T15,T16 

 LINE       52
 SUB-EXPRESSION (rptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT8,T15,T16 

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered 

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       68
 EXPRESSION (full_o ? (2'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o)))))
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered 

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3 

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3
Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
Branches 13 11 84.62
TERNARY 68 3 1 33.33
IF 113 5 5 100.00
IF 125 5 5 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	68	(full_o) ? 
-2-:	68	((wptr_wrap_msb == rptr_wrap_msb)) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T1,T2,T3
0 0 Not Covered 



	LineNo.	Expression
-1-:	113	if ((!rst_ni))
-2-:	115	if (clr_i)
-3-:	117	if (wptr_wrap_set)
-4-:	119	if (incr_wptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T8,T15,T16
0 0 0 1 Covered T8,T15,T16
0 0 0 0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	125	if ((!rst_ni))
-2-:	127	if (clr_i)
-3-:	129	if (rptr_wrap_set)
-4-:	131	if (incr_rptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T8,T15,T16
0 0 0 1 Covered T8,T15,T16
0 0 0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
TOTAL2727100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6811100.00
ALWAYS11388100.00
ALWAYS12588100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
41 1 1
42 1 1
46 1 1
47 1 1
51 1 1
52 1 1
55 1 1
56 1 1
59 1 1
61 1 1
68 1 1
113 1 1
114 1 1
115 1 1
116 1 1
117 1 1
118 1 1
119 1 1
120 1 1
MISSING_ELSE
125 1 1
126 1 1
127 1 1
128 1 1
129 1 1
130 1 1
131 1 1
132 1 1
MISSING_ELSE

Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.u_fifo_cnt
TotalCoveredPercent
Conditions201890.00
Logical201890.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT8,T9,T14
10CoveredT8,T9,T14
11CoveredT8,T9,T14 

 LINE       51
 SUB-EXPRESSION (wptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT8,T9,T14 

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT8,T9,T14
10CoveredT8,T9,T14
11CoveredT8,T9,T14 

 LINE       52
 SUB-EXPRESSION (rptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT8,T9,T14 

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered 

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       68
 EXPRESSION (full_o ? (2'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o)))))
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered 

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0CoveredT17,T160,T84
1CoveredT1,T2,T3 

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0CoveredT17,T160,T84
1CoveredT1,T2,T3
Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
Branches 13 12 92.31
TERNARY 68 3 2 66.67
IF 113 5 5 100.00
IF 125 5 5 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	68	(full_o) ? 
-2-:	68	((wptr_wrap_msb == rptr_wrap_msb)) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T1,T2,T3
0 0 Covered T17,T160,T84 



	LineNo.	Expression
-1-:	113	if ((!rst_ni))
-2-:	115	if (clr_i)
-3-:	117	if (wptr_wrap_set)
-4-:	119	if (incr_wptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T8,T9,T14
0 0 0 1 Covered T8,T9,T14
0 0 0 0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	125	if ((!rst_ni))
-2-:	127	if (clr_i)
-3-:	129	if (rptr_wrap_set)
-4-:	131	if (incr_rptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T8,T9,T14
0 0 0 1 Covered T8,T9,T14
0 0 0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
TOTAL2727100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6811100.00
ALWAYS11388100.00
ALWAYS12588100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
41 1 1
42 1 1
46 1 1
47 1 1
51 1 1
52 1 1
55 1 1
56 1 1
59 1 1
61 1 1
68 1 1
113 1 1
114 1 1
115 1 1
116 1 1
117 1 1
118 1 1
119 1 1
120 1 1
MISSING_ELSE
125 1 1
126 1 1
127 1 1
128 1 1
129 1 1
130 1 1
131 1 1
132 1 1
MISSING_ELSE

Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.u_fifo_cnt
TotalCoveredPercent
Conditions201890.00
Logical201890.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT1,T4,T5
10CoveredT1,T4,T5
11CoveredT1,T4,T5 

 LINE       51
 SUB-EXPRESSION (wptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5 

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT1,T4,T5
10CoveredT1,T4,T5
11CoveredT1,T4,T5 

 LINE       52
 SUB-EXPRESSION (rptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5 

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered 

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       68
 EXPRESSION (full_o ? (2'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o)))))
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered 

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0CoveredT5,T64,T75
1CoveredT1,T2,T3 

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0CoveredT5,T64,T75
1CoveredT1,T2,T3
Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
Branches 13 12 92.31
TERNARY 68 3 2 66.67
IF 113 5 5 100.00
IF 125 5 5 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	68	(full_o) ? 
-2-:	68	((wptr_wrap_msb == rptr_wrap_msb)) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T1,T2,T3
0 0 Covered T5,T64,T75 



	LineNo.	Expression
-1-:	113	if ((!rst_ni))
-2-:	115	if (clr_i)
-3-:	117	if (wptr_wrap_set)
-4-:	119	if (incr_wptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T1,T4,T5
0 0 0 1 Covered T1,T4,T5
0 0 0 0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	125	if ((!rst_ni))
-2-:	127	if (clr_i)
-3-:	129	if (rptr_wrap_set)
-4-:	131	if (incr_rptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T1,T4,T5
0 0 0 1 Covered T1,T4,T5
0 0 0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
TOTAL2727100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6811100.00
ALWAYS11388100.00
ALWAYS12588100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
41 1 1
42 1 1
46 1 1
47 1 1
51 1 1
52 1 1
55 1 1
56 1 1
59 1 1
61 1 1
68 1 1
113 1 1
114 1 1
115 1 1
116 1 1
117 1 1
118 1 1
119 1 1
120 1 1
MISSING_ELSE
125 1 1
126 1 1
127 1 1
128 1 1
129 1 1
130 1 1
131 1 1
132 1 1
MISSING_ELSE

Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.u_fifo_cnt
TotalCoveredPercent
Conditions201890.00
Logical201890.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       51
 SUB-EXPRESSION (wptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       52
 SUB-EXPRESSION (rptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered 

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       68
 EXPRESSION (full_o ? (2'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o)))))
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered 

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0CoveredT87,T188,T228
1CoveredT1,T2,T3 

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0CoveredT87,T188,T228
1CoveredT1,T2,T3
Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
Branches 13 12 92.31
TERNARY 68 3 2 66.67
IF 113 5 5 100.00
IF 125 5 5 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	68	(full_o) ? 
-2-:	68	((wptr_wrap_msb == rptr_wrap_msb)) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T1,T2,T3
0 0 Covered T87,T188,T228 



	LineNo.	Expression
-1-:	113	if ((!rst_ni))
-2-:	115	if (clr_i)
-3-:	117	if (wptr_wrap_set)
-4-:	119	if (incr_wptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T1,T2,T3
0 0 0 1 Covered T1,T2,T3
0 0 0 0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	125	if ((!rst_ni))
-2-:	127	if (clr_i)
-3-:	129	if (rptr_wrap_set)
-4-:	131	if (incr_rptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T1,T2,T3
0 0 0 1 Covered T1,T2,T3
0 0 0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
TOTAL2727100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6811100.00
ALWAYS11388100.00
ALWAYS12588100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
41 1 1
42 1 1
46 1 1
47 1 1
51 1 1
52 1 1
55 1 1
56 1 1
59 1 1
61 1 1
68 1 1
113 1 1
114 1 1
115 1 1
116 1 1
117 1 1
118 1 1
119 1 1
120 1 1
MISSING_ELSE
125 1 1
126 1 1
127 1 1
128 1 1
129 1 1
130 1 1
131 1 1
132 1 1
MISSING_ELSE

Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.u_fifo_cnt
TotalCoveredPercent
Conditions2020100.00
Logical2020100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT8,T9,T14
10CoveredT8,T9,T14
11CoveredT8,T9,T14 

 LINE       51
 SUB-EXPRESSION (wptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT8,T9,T14 

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT8,T14,T15
10CoveredT8,T14,T15
11CoveredT8,T14,T15 

 LINE       52
 SUB-EXPRESSION (rptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT8,T14,T15 

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT8,T9,T14 

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       68
 EXPRESSION (full_o ? (2'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o)))))
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT8,T9,T14 

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0CoveredT8,T14,T15
1CoveredT1,T2,T3 

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0CoveredT8,T14,T15
1CoveredT1,T2,T3
Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
Branches 13 13 100.00
TERNARY 68 3 3 100.00
IF 113 5 5 100.00
IF 125 5 5 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	68	(full_o) ? 
-2-:	68	((wptr_wrap_msb == rptr_wrap_msb)) ?

Branches:
-1--2-StatusTests
1 - Covered T8,T9,T14
0 1 Covered T1,T2,T3
0 0 Covered T8,T14,T15 



	LineNo.	Expression
-1-:	113	if ((!rst_ni))
-2-:	115	if (clr_i)
-3-:	117	if (wptr_wrap_set)
-4-:	119	if (incr_wptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T8,T9,T14
0 0 0 1 Covered T8,T9,T14
0 0 0 0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	125	if ((!rst_ni))
-2-:	127	if (clr_i)
-3-:	129	if (rptr_wrap_set)
-4-:	131	if (incr_rptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T8,T14,T15
0 0 0 1 Covered T8,T14,T15
0 0 0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_sram_ptrs
Line No.TotalCoveredPercent
TOTAL2727100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6811100.00
ALWAYS11388100.00
ALWAYS12588100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
41 1 1
42 1 1
46 1 1
47 1 1
51 1 1
52 1 1
55 1 1
56 1 1
59 1 1
61 1 1
68 1 1
113 1 1
114 1 1
115 1 1
116 1 1
117 1 1
118 1 1
119 1 1
120 1 1
MISSING_ELSE
125 1 1
126 1 1
127 1 1
128 1 1
129 1 1
130 1 1
131 1 1
132 1 1
MISSING_ELSE

Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_sram_ptrs
TotalCoveredPercent
Conditions2020100.00
Logical2020100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 6'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT8,T14,T16
10CoveredT8,T9,T14
11CoveredT8,T14,T16 

 LINE       51
 SUB-EXPRESSION (wptr_o == 6'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT8,T14,T16 

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 6'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT8,T14,T16
10CoveredT8,T14,T16
11CoveredT8,T14,T16 

 LINE       52
 SUB-EXPRESSION (rptr_o == 6'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT8,T14,T16 

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT14,T17,T24 

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       68
 EXPRESSION (full_o ? (6'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((6'(wptr_o) - 6'(rptr_o))) : (((6'(Depth) - 6'(rptr_o)) + 6'(wptr_o)))))
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT14,T17,T24 

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((6'(wptr_o) - 6'(rptr_o))) : (((6'(Depth) - 6'(rptr_o)) + 6'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0CoveredT8,T14,T16
1CoveredT1,T2,T3 

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0CoveredT8,T14,T16
1CoveredT1,T2,T3
Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_sram_ptrs
Line No.TotalCoveredPercent
Branches 13 13 100.00
TERNARY 68 3 3 100.00
IF 113 5 5 100.00
IF 125 5 5 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	68	(full_o) ? 
-2-:	68	((wptr_wrap_msb == rptr_wrap_msb)) ?

Branches:
-1--2-StatusTests
1 - Covered T14,T17,T24
0 1 Covered T1,T2,T3
0 0 Covered T8,T14,T16 



	LineNo.	Expression
-1-:	113	if ((!rst_ni))
-2-:	115	if (clr_i)
-3-:	117	if (wptr_wrap_set)
-4-:	119	if (incr_wptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T8,T14,T16
0 0 0 1 Covered T8,T9,T14
0 0 0 0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	125	if ((!rst_ni))
-2-:	127	if (clr_i)
-3-:	129	if (rptr_wrap_set)
-4-:	131	if (incr_rptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T8,T14,T16
0 0 0 1 Covered T8,T14,T16
0 0 0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
TOTAL2727100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6811100.00
ALWAYS11388100.00
ALWAYS12588100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
41 1 1
42 1 1
46 1 1
47 1 1
51 1 1
52 1 1
55 1 1
56 1 1
59 1 1
61 1 1
68 1 1
113 1 1
114 1 1
115 1 1
116 1 1
117 1 1
118 1 1
119 1 1
120 1 1
MISSING_ELSE
125 1 1
126 1 1
127 1 1
128 1 1
129 1 1
130 1 1
131 1 1
132 1 1
MISSING_ELSE

Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.u_fifo_cnt
TotalCoveredPercent
Conditions2020100.00
Logical2020100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT8,T15,T16
10CoveredT8,T15,T16
11CoveredT8,T15,T16 

 LINE       51
 SUB-EXPRESSION (wptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT8,T15,T16 

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT8,T16,T40
10CoveredT8,T16,T40
11CoveredT8,T16,T40 

 LINE       52
 SUB-EXPRESSION (rptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT8,T16,T40 

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT15,T40,T17 

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       68
 EXPRESSION (full_o ? (2'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o)))))
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT15,T40,T17 

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0CoveredT8,T16,T40
1CoveredT1,T2,T3 

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0CoveredT8,T16,T40
1CoveredT1,T2,T3
Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
Branches 13 13 100.00
TERNARY 68 3 3 100.00
IF 113 5 5 100.00
IF 125 5 5 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	68	(full_o) ? 
-2-:	68	((wptr_wrap_msb == rptr_wrap_msb)) ?

Branches:
-1--2-StatusTests
1 - Covered T15,T40,T17
0 1 Covered T1,T2,T3
0 0 Covered T8,T16,T40 



	LineNo.	Expression
-1-:	113	if ((!rst_ni))
-2-:	115	if (clr_i)
-3-:	117	if (wptr_wrap_set)
-4-:	119	if (incr_wptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T8,T15,T16
0 0 0 1 Covered T8,T15,T16
0 0 0 0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	125	if ((!rst_ni))
-2-:	127	if (clr_i)
-3-:	129	if (rptr_wrap_set)
-4-:	131	if (incr_rptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T8,T16,T40
0 0 0 1 Covered T8,T16,T40
0 0 0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_sram_ptrs
Line No.TotalCoveredPercent
TOTAL2727100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6811100.00
ALWAYS11388100.00
ALWAYS12588100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
41 1 1
42 1 1
46 1 1
47 1 1
51 1 1
52 1 1
55 1 1
56 1 1
59 1 1
61 1 1
68 1 1
113 1 1
114 1 1
115 1 1
116 1 1
117 1 1
118 1 1
119 1 1
120 1 1
MISSING_ELSE
125 1 1
126 1 1
127 1 1
128 1 1
129 1 1
130 1 1
131 1 1
132 1 1
MISSING_ELSE

Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_sram_ptrs
TotalCoveredPercent
Conditions2020100.00
Logical2020100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 6'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT15,T40,T17
10CoveredT15,T40,T17
11CoveredT15,T40,T17 

 LINE       51
 SUB-EXPRESSION (wptr_o == 6'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT15,T40,T17 

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 6'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT40,T17,T49
10CoveredT40,T17,T49
11CoveredT40,T17,T49 

 LINE       52
 SUB-EXPRESSION (rptr_o == 6'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT40,T17,T49 

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT15,T40,T17 

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       68
 EXPRESSION (full_o ? (6'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((6'(wptr_o) - 6'(rptr_o))) : (((6'(Depth) - 6'(rptr_o)) + 6'(wptr_o)))))
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT15,T40,T17 

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((6'(wptr_o) - 6'(rptr_o))) : (((6'(Depth) - 6'(rptr_o)) + 6'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0CoveredT40,T17,T49
1CoveredT1,T2,T3 

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0CoveredT40,T17,T49
1CoveredT1,T2,T3
Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_sram_ptrs
Line No.TotalCoveredPercent
Branches 13 13 100.00
TERNARY 68 3 3 100.00
IF 113 5 5 100.00
IF 125 5 5 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	68	(full_o) ? 
-2-:	68	((wptr_wrap_msb == rptr_wrap_msb)) ?

Branches:
-1--2-StatusTests
1 - Covered T15,T40,T17
0 1 Covered T1,T2,T3
0 0 Covered T40,T17,T49 



	LineNo.	Expression
-1-:	113	if ((!rst_ni))
-2-:	115	if (clr_i)
-3-:	117	if (wptr_wrap_set)
-4-:	119	if (incr_wptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T15,T40,T17
0 0 0 1 Covered T15,T40,T17
0 0 0 0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	125	if ((!rst_ni))
-2-:	127	if (clr_i)
-3-:	129	if (rptr_wrap_set)
-4-:	131	if (incr_rptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T40,T17,T49
0 0 0 1 Covered T40,T17,T49
0 0 0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
TOTAL2727100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6811100.00
ALWAYS11388100.00
ALWAYS12588100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
41 1 1
42 1 1
46 1 1
47 1 1
51 1 1
52 1 1
55 1 1
56 1 1
59 1 1
61 1 1
68 1 1
113 1 1
114 1 1
115 1 1
116 1 1
117 1 1
118 1 1
119 1 1
120 1 1
MISSING_ELSE
125 1 1
126 1 1
127 1 1
128 1 1
129 1 1
130 1 1
131 1 1
132 1 1
MISSING_ELSE

Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.u_fifo_cnt
TotalCoveredPercent
Conditions2020100.00
Logical2020100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT1,T4,T5
10CoveredT1,T4,T5
11CoveredT1,T4,T5 

 LINE       51
 SUB-EXPRESSION (wptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5 

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT1,T4,T5
10CoveredT1,T4,T5
11CoveredT1,T4,T5 

 LINE       52
 SUB-EXPRESSION (rptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5 

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5 

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       68
 EXPRESSION (full_o ? (2'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o)))))
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5 

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT1,T2,T3 

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT1,T2,T3
Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
Branches 13 13 100.00
TERNARY 68 3 3 100.00
IF 113 5 5 100.00
IF 125 5 5 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	68	(full_o) ? 
-2-:	68	((wptr_wrap_msb == rptr_wrap_msb)) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T5
0 1 Covered T1,T2,T3
0 0 Covered T1,T4,T5 



	LineNo.	Expression
-1-:	113	if ((!rst_ni))
-2-:	115	if (clr_i)
-3-:	117	if (wptr_wrap_set)
-4-:	119	if (incr_wptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T1,T4,T5
0 0 0 1 Covered T1,T4,T5
0 0 0 0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	125	if ((!rst_ni))
-2-:	127	if (clr_i)
-3-:	129	if (rptr_wrap_set)
-4-:	131	if (incr_rptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T1,T4,T5
0 0 0 1 Covered T1,T4,T5
0 0 0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_sram_ptrs
Line No.TotalCoveredPercent
TOTAL2727100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6811100.00
ALWAYS11388100.00
ALWAYS12588100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
41 1 1
42 1 1
46 1 1
47 1 1
51 1 1
52 1 1
55 1 1
56 1 1
59 1 1
61 1 1
68 1 1
113 1 1
114 1 1
115 1 1
116 1 1
117 1 1
118 1 1
119 1 1
120 1 1
MISSING_ELSE
125 1 1
126 1 1
127 1 1
128 1 1
129 1 1
130 1 1
131 1 1
132 1 1
MISSING_ELSE

Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_sram_ptrs
TotalCoveredPercent
Conditions2020100.00
Logical2020100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 6'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT5,T64,T74
10CoveredT1,T4,T5
11CoveredT5,T64,T74 

 LINE       51
 SUB-EXPRESSION (wptr_o == 6'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T64,T74 

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 6'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT5,T64,T74
10CoveredT1,T4,T5
11CoveredT5,T64,T74 

 LINE       52
 SUB-EXPRESSION (rptr_o == 6'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T64,T74 

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT168,T55,T56 

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       68
 EXPRESSION (full_o ? (6'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((6'(wptr_o) - 6'(rptr_o))) : (((6'(Depth) - 6'(rptr_o)) + 6'(wptr_o)))))
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT168,T55,T56 

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((6'(wptr_o) - 6'(rptr_o))) : (((6'(Depth) - 6'(rptr_o)) + 6'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0CoveredT5,T64,T74
1CoveredT1,T2,T3 

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0CoveredT5,T64,T74
1CoveredT1,T2,T3
Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_sram_ptrs
Line No.TotalCoveredPercent
Branches 13 13 100.00
TERNARY 68 3 3 100.00
IF 113 5 5 100.00
IF 125 5 5 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	68	(full_o) ? 
-2-:	68	((wptr_wrap_msb == rptr_wrap_msb)) ?

Branches:
-1--2-StatusTests
1 - Covered T168,T55,T56
0 1 Covered T1,T2,T3
0 0 Covered T5,T64,T74 



	LineNo.	Expression
-1-:	113	if ((!rst_ni))
-2-:	115	if (clr_i)
-3-:	117	if (wptr_wrap_set)
-4-:	119	if (incr_wptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T5,T64,T74
0 0 0 1 Covered T1,T4,T5
0 0 0 0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	125	if ((!rst_ni))
-2-:	127	if (clr_i)
-3-:	129	if (rptr_wrap_set)
-4-:	131	if (incr_rptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T5,T64,T74
0 0 0 1 Covered T1,T4,T5
0 0 0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
TOTAL2727100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6811100.00
ALWAYS11388100.00
ALWAYS12588100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
41 1 1
42 1 1
46 1 1
47 1 1
51 1 1
52 1 1
55 1 1
56 1 1
59 1 1
61 1 1
68 1 1
113 1 1
114 1 1
115 1 1
116 1 1
117 1 1
118 1 1
119 1 1
120 1 1
MISSING_ELSE
125 1 1
126 1 1
127 1 1
128 1 1
129 1 1
130 1 1
131 1 1
132 1 1
MISSING_ELSE

Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.u_fifo_cnt
TotalCoveredPercent
Conditions2020100.00
Logical2020100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       51
 SUB-EXPRESSION (wptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       52
 SUB-EXPRESSION (rptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       68
 EXPRESSION (full_o ? (2'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o)))))
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3
Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
Branches 13 13 100.00
TERNARY 68 3 3 100.00
IF 113 5 5 100.00
IF 125 5 5 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	68	(full_o) ? 
-2-:	68	((wptr_wrap_msb == rptr_wrap_msb)) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	113	if ((!rst_ni))
-2-:	115	if (clr_i)
-3-:	117	if (wptr_wrap_set)
-4-:	119	if (incr_wptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T1,T2,T3
0 0 0 1 Covered T1,T2,T3
0 0 0 0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	125	if ((!rst_ni))
-2-:	127	if (clr_i)
-3-:	129	if (rptr_wrap_set)
-4-:	131	if (incr_rptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T1,T2,T3
0 0 0 1 Covered T1,T2,T3
0 0 0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_sram_ptrs
Line No.TotalCoveredPercent
TOTAL2727100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6811100.00
ALWAYS11388100.00
ALWAYS12588100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
41 1 1
42 1 1
46 1 1
47 1 1
51 1 1
52 1 1
55 1 1
56 1 1
59 1 1
61 1 1
68 1 1
113 1 1
114 1 1
115 1 1
116 1 1
117 1 1
118 1 1
119 1 1
120 1 1
MISSING_ELSE
125 1 1
126 1 1
127 1 1
128 1 1
129 1 1
130 1 1
131 1 1
132 1 1
MISSING_ELSE

Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_sram_ptrs
TotalCoveredPercent
Conditions2020100.00
Logical2020100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 9'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT2,T3,T10
10CoveredT2,T3,T5
11CoveredT2,T3,T10 

 LINE       51
 SUB-EXPRESSION (wptr_o == 9'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T10 

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 9'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT2,T3,T10
10CoveredT2,T3,T5
11CoveredT2,T3,T10 

 LINE       52
 SUB-EXPRESSION (rptr_o == 9'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T10 

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT10,T54,T60 

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       68
 EXPRESSION (full_o ? (9'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((9'(wptr_o) - 9'(rptr_o))) : (((9'(Depth) - 9'(rptr_o)) + 9'(wptr_o)))))
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT10,T54,T60 

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((9'(wptr_o) - 9'(rptr_o))) : (((9'(Depth) - 9'(rptr_o)) + 9'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0CoveredT2,T3,T10
1CoveredT1,T2,T3 

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0CoveredT2,T3,T10
1CoveredT1,T2,T3
Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_sram_ptrs
Line No.TotalCoveredPercent
Branches 13 13 100.00
TERNARY 68 3 3 100.00
IF 113 5 5 100.00
IF 125 5 5 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	68	(full_o) ? 
-2-:	68	((wptr_wrap_msb == rptr_wrap_msb)) ?

Branches:
-1--2-StatusTests
1 - Covered T10,T54,T60
0 1 Covered T1,T2,T3
0 0 Covered T2,T3,T10 



	LineNo.	Expression
-1-:	113	if ((!rst_ni))
-2-:	115	if (clr_i)
-3-:	117	if (wptr_wrap_set)
-4-:	119	if (incr_wptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T2,T3,T10
0 0 0 1 Covered T2,T3,T5
0 0 0 0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	125	if ((!rst_ni))
-2-:	127	if (clr_i)
-3-:	129	if (rptr_wrap_set)
-4-:	131	if (incr_rptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T2,T3,T10
0 0 0 1 Covered T2,T3,T5
0 0 0 0 Covered T1,T2,T3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%