Toggle Coverage for Module :
prim_onehot_check
| Total | Covered | Percent |
Totals |
5 |
5 |
100.00 |
Total Bits |
56 |
56 |
100.00 |
Total Bits 0->1 |
28 |
28 |
100.00 |
Total Bits 1->0 |
28 |
28 |
100.00 |
| | | |
Ports |
5 |
5 |
100.00 |
Port Bits |
56 |
56 |
100.00 |
Port Bits 0->1 |
28 |
28 |
100.00 |
Port Bits 1->0 |
28 |
28 |
100.00 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
rst_ni |
Yes |
Yes |
T17,T20,T11 |
Yes |
T1,T2,T3 |
INPUT |
oh_i[4:0] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
INPUT |
oh_i[6:5] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
oh_i[10:7] |
Yes |
Yes |
T8,*T9,*T14 |
Yes |
T8,T9,T14 |
INPUT |
oh_i[12:11] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
oh_i[13] |
Yes |
Yes |
*T99,*T100,*T83 |
Yes |
T99,T100,T83 |
INPUT |
oh_i[14] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
oh_i[21:15] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
oh_i[22] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
oh_i[25:23] |
Yes |
Yes |
*T1,*T4,*T5 |
Yes |
T1,T4,T5 |
INPUT |
oh_i[26] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
oh_i[27] |
Yes |
Yes |
*T2,*T5,*T52 |
Yes |
T2,T5,T52 |
INPUT |
oh_i[28] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
oh_i[31:29] |
Yes |
Yes |
T26,T27,T28 |
Yes |
T26,T27,T28 |
INPUT |
addr_i[4:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
en_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
err_o |
Yes |
Yes |
T192,T193,T194 |
Yes |
T192,T193,T194 |
OUTPUT |
*Tests covering at least one bit in the range