Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.48	100.00	100.00	93.91			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	399088533	0	0	0
ctrl_rd_A	399088533	1039	0	0
host_fifo_config_rd_A	399088533	2441	0	0
host_nack_handler_timeout_rd_A	399088533	954	0	0
host_timeout_ctrl_rd_A	399088533	920	0	0
intr_enable_rd_A	399088533	1751	0	0
ovrd_rd_A	399088533	1615	0	0
target_fifo_config_rd_A	399088533	814	0	0
target_id_rd_A	399088533	1036	0	0
target_timeout_ctrl_rd_A	399088533	824	0	0
timeout_ctrl_rd_A	399088533	875	0	0
timing0_rd_A	399088533	819	0	0
timing1_rd_A	399088533	808	0	0
timing2_rd_A	399088533	820	0	0
timing3_rd_A	399088533	866	0	0
timing4_rd_A	399088533	951	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399088533	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399088533	1039	0	0
T102	13009	14	0	0
T103	2425	5	0	0
T104	1295	31	0	0
T105	6437	21	0	0
T106	1929	29	0	0
T107	2285	11	0	0
T108	3743	65	0	0
T109	1948	9	0	0
T110	2448	10	0	0
T111	2235	51	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399088533	2441	0	0
T19	298600	0	0	0
T27	47547	0	0	0
T28	22406	0	0	0
T112	365807	119	0	0
T113	0	87	0	0
T114	0	222	0	0
T115	0	84	0	0
T116	0	226	0	0
T117	0	199	0	0
T118	0	145	0	0
T119	0	140	0	0
T120	0	77	0	0
T121	0	281	0	0
T122	3359	0	0	0
T123	122924	0	0	0
T124	1294	0	0	0
T125	13738	0	0	0
T126	69704	0	0	0
T127	34111	0	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399088533	954	0	0
T102	13009	27	0	0
T103	2425	5	0	0
T104	1295	2	0	0
T105	6437	49	0	0
T106	1929	14	0	0
T107	2285	2	0	0
T108	3743	11	0	0
T109	1948	18	0	0
T110	2448	4	0	0
T111	2235	15	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399088533	920	0	0
T102	13009	10	0	0
T103	2425	15	0	0
T104	1295	1	0	0
T105	6437	37	0	0
T106	1929	4	0	0
T107	2285	10	0	0
T108	3743	12	0	0
T109	1948	2	0	0
T110	2448	14	0	0
T128	3194	18	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399088533	1751	0	0
T44	568027	0	0	0
T102	0	18	0	0
T103	0	7	0	0
T104	0	5	0	0
T105	0	139	0	0
T129	569767	27	0	0
T130	0	20	0	0
T131	0	41	0	0
T132	0	37	0	0
T133	0	14	0	0
T134	0	16	0	0
T135	140312	0	0	0
T136	39111	0	0	0
T137	352213	0	0	0
T138	49718	0	0	0
T139	2666	0	0	0
T140	33864	0	0	0
T141	11971	0	0	0
T142	107984	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399088533	1615	0	0
T63	4271	0	0	0
T68	80940	0	0	0
T100	1693	31	0	0
T143	0	67	0	0
T144	0	47	0	0
T145	0	33	0	0
T146	0	71	0	0
T147	0	42	0	0
T148	0	63	0	0
T149	0	41	0	0
T150	0	46	0	0
T151	0	40	0	0
T152	22964	0	0	0
T153	13908	0	0	0
T154	23077	0	0	0
T155	32124	0	0	0
T156	118095	0	0	0
T157	1455	0	0	0
T158	2347	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399088533	814	0	0
T102	13009	14	0	0
T103	2425	2	0	0
T104	1295	11	0	0
T105	6437	27	0	0
T106	1929	6	0	0
T107	2285	10	0	0
T108	3743	19	0	0
T109	1948	9	0	0
T110	2448	9	0	0
T128	3194	1	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399088533	1036	0	0
T102	13009	23	0	0
T103	2425	13	0	0
T104	1295	18	0	0
T105	6437	52	0	0
T106	1929	30	0	0
T107	2285	4	0	0
T108	3743	38	0	0
T109	1948	11	0	0
T110	2448	7	0	0
T128	3194	12	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399088533	824	0	0
T102	13009	4	0	0
T103	2425	16	0	0
T104	1295	9	0	0
T105	6437	42	0	0
T106	1929	9	0	0
T107	2285	13	0	0
T108	3743	12	0	0
T109	1948	4	0	0
T110	2448	6	0	0
T128	3194	8	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399088533	875	0	0
T102	13009	21	0	0
T103	2425	9	0	0
T105	6437	57	0	0
T106	1929	1	0	0
T107	2285	4	0	0
T108	3743	35	0	0
T109	1948	17	0	0
T110	2448	8	0	0
T111	2235	15	0	0
T159	3950	20	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399088533	819	0	0
T102	13009	20	0	0
T103	2425	21	0	0
T104	1295	2	0	0
T105	6437	25	0	0
T106	1929	5	0	0
T107	2285	5	0	0
T108	3743	21	0	0
T109	1948	4	0	0
T110	2448	1	0	0
T128	3194	32	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399088533	808	0	0
T102	13009	14	0	0
T103	2425	5	0	0
T104	1295	4	0	0
T105	6437	14	0	0
T106	1929	9	0	0
T107	2285	9	0	0
T108	3743	20	0	0
T109	1948	6	0	0
T110	2448	10	0	0
T111	2235	12	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399088533	820	0	0
T102	13009	21	0	0
T103	2425	19	0	0
T105	6437	14	0	0
T106	1929	11	0	0
T107	2285	6	0	0
T108	3743	12	0	0
T109	1948	13	0	0
T110	2448	3	0	0
T111	2235	16	0	0
T128	3194	7	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399088533	866	0	0
T102	13009	3	0	0
T103	2425	8	0	0
T104	1295	3	0	0
T105	6437	24	0	0
T106	1929	5	0	0
T107	2285	7	0	0
T108	3743	15	0	0
T109	1948	3	0	0
T110	2448	13	0	0
T128	3194	11	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399088533	951	0	0
T102	13009	18	0	0
T103	2425	18	0	0
T104	1295	3	0	0
T105	6437	55	0	0
T106	1929	5	0	0
T107	2285	12	0	0
T108	3743	21	0	0
T109	1948	14	0	0
T110	2448	10	0	0
T128	3194	19	0	0