Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	28966524	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

7616620

1

T1

186

T2

28

T3

434

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	35742939	1			T1	8214		T2	4		T3	963
values[0x0]	419926	1			T1	112		T2	23		T3	199
values[0x1]	420279	1			T1	130		T2	17		T3	198

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	20277152	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

16305992

1

T1

4189

T2

30

T3

691

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	130049	1			T2	2		T3	6		T4	69
valid_sources[0x01]	149177	1			T4	84		T5	5		T7	96
valid_sources[0x02]	144733	1			T3	8		T4	64		T5	2
valid_sources[0x03]	138613	1			T3	7		T4	58		T5	3
valid_sources[0x04]	142957	1			T3	3		T4	94		T5	3
valid_sources[0x05]	159611	1			T2	1		T3	2		T4	86
valid_sources[0x06]	135882	1			T3	2		T4	89		T5	6
valid_sources[0x07]	448477	1			T3	8		T4	82		T5	4
valid_sources[0x08]	124799	1			T3	2		T4	87		T5	8
valid_sources[0x09]	143643	1			T4	96		T5	3		T8	6
valid_sources[0x0a]	134648	1			T3	3		T4	67		T5	4
valid_sources[0x0b]	138431	1			T3	2		T4	77		T5	2
valid_sources[0x0c]	142213	1			T3	3		T4	72		T5	7
valid_sources[0x0d]	134900	1			T4	71		T5	5		T8	1
valid_sources[0x0e]	125677	1			T2	1		T3	2		T4	93
valid_sources[0x0f]	135880	1			T3	8		T4	71		T5	3
valid_sources[0x10]	132800	1			T3	7		T4	75		T5	4
valid_sources[0x11]	132022	1			T2	1		T3	5		T4	85
valid_sources[0x12]	143569	1			T3	5		T4	71		T5	2
valid_sources[0x13]	135469	1			T3	4		T4	73		T5	3
valid_sources[0x14]	122937	1			T3	4		T4	77		T5	6
valid_sources[0x15]	172329	1			T3	7		T4	98		T5	3
valid_sources[0x16]	155190	1			T3	11		T4	68		T5	2
valid_sources[0x17]	135115	1			T4	72		T5	3		T7	6
valid_sources[0x18]	139525	1			T3	4		T4	75		T5	4
valid_sources[0x19]	157804	1			T1	16		T3	1		T4	71
valid_sources[0x1a]	144528	1			T3	6		T4	87		T5	9
valid_sources[0x1b]	139503	1			T3	7		T4	89		T5	6
valid_sources[0x1c]	140543	1			T4	74		T5	1		T8	7
valid_sources[0x1d]	158347	1			T3	11		T4	75		T5	1
valid_sources[0x1e]	143029	1			T3	15		T4	77		T5	9
valid_sources[0x1f]	151803	1			T3	2		T4	69		T5	8
valid_sources[0x20]	129925	1			T3	2		T4	67		T5	4
valid_sources[0x21]	134206	1			T2	1		T3	4		T4	97
valid_sources[0x22]	131464	1			T3	4		T4	87		T5	6
valid_sources[0x23]	143065	1			T3	8		T4	84		T5	2
valid_sources[0x24]	134682	1			T3	1		T4	72		T5	6
valid_sources[0x25]	144197	1			T3	6		T4	69		T5	5
valid_sources[0x26]	138567	1			T3	5		T4	80		T5	6
valid_sources[0x27]	148525	1			T3	4		T4	87		T5	4
valid_sources[0x28]	129148	1			T3	5		T4	80		T5	2
valid_sources[0x29]	134314	1			T4	86		T5	4		T8	4
valid_sources[0x2a]	126304	1			T1	86		T2	1		T3	3
valid_sources[0x2b]	141187	1			T2	1		T3	11		T4	88
valid_sources[0x2c]	133670	1			T3	1		T4	75		T5	5
valid_sources[0x2d]	139594	1			T2	1		T3	5		T4	83
valid_sources[0x2e]	161547	1			T3	1		T4	60		T5	6
valid_sources[0x2f]	131969	1			T3	7		T4	70		T5	4
valid_sources[0x30]	133025	1			T3	4		T4	95		T5	2
valid_sources[0x31]	140671	1			T3	1		T4	78		T5	8
valid_sources[0x32]	130220	1			T3	7		T4	83		T5	1
valid_sources[0x33]	132151	1			T3	7		T4	72		T5	1
valid_sources[0x34]	151759	1			T3	8		T4	82		T5	7
valid_sources[0x35]	156721	1			T3	4		T4	81		T5	4
valid_sources[0x36]	171921	1			T3	7		T4	104		T5	5
valid_sources[0x37]	139020	1			T3	9		T4	68		T5	3
valid_sources[0x38]	147904	1			T3	5		T4	72		T5	5
valid_sources[0x39]	140154	1			T4	73		T5	4		T7	6
valid_sources[0x3a]	150025	1			T3	2		T4	99		T5	4
valid_sources[0x3b]	149678	1			T4	64		T5	1		T8	8
valid_sources[0x3c]	140372	1			T4	91		T5	4		T8	7
valid_sources[0x3d]	131699	1			T3	14		T4	66		T5	6
valid_sources[0x3e]	148429	1			T4	65		T5	7		T8	6
valid_sources[0x3f]	128920	1			T3	6		T4	76		T5	3
valid_sources[0x40]	127429	1			T3	9		T4	81		T5	5
valid_sources[0x41]	132485	1			T3	10		T4	93		T5	7
valid_sources[0x42]	131034	1			T3	9		T4	100		T5	6
valid_sources[0x43]	146103	1			T3	7		T4	85		T5	3
valid_sources[0x44]	136633	1			T3	6		T4	87		T5	7
valid_sources[0x45]	139711	1			T1	42		T3	8		T4	80
valid_sources[0x46]	131761	1			T3	5		T4	65		T5	5
valid_sources[0x47]	147038	1			T3	12		T4	77		T5	3
valid_sources[0x48]	125461	1			T3	9		T4	82		T5	5
valid_sources[0x49]	134745	1			T3	2		T4	90		T5	1
valid_sources[0x4a]	161162	1			T3	4		T4	73		T5	6
valid_sources[0x4b]	128806	1			T3	13		T4	77		T5	5
valid_sources[0x4c]	142054	1			T3	4		T4	78		T5	4
valid_sources[0x4d]	129763	1			T2	1		T3	8		T4	84
valid_sources[0x4e]	132240	1			T2	2		T3	9		T4	83
valid_sources[0x4f]	154030	1			T3	8		T4	79		T5	6
valid_sources[0x50]	137186	1			T3	6		T4	81		T5	4
valid_sources[0x51]	164818	1			T3	9		T4	100		T5	1
valid_sources[0x52]	127848	1			T3	4		T4	56		T5	3
valid_sources[0x53]	163286	1			T3	2		T4	75		T5	6
valid_sources[0x54]	146579	1			T3	3		T4	62		T5	1
valid_sources[0x55]	146591	1			T3	2		T4	80		T5	2
valid_sources[0x56]	150539	1			T2	2		T3	2		T4	57
valid_sources[0x57]	135325	1			T3	15		T4	80		T5	3
valid_sources[0x58]	137095	1			T3	1		T4	64		T5	8
valid_sources[0x59]	142746	1			T3	5		T4	62		T5	5
valid_sources[0x5a]	130500	1			T3	4		T4	92		T5	4
valid_sources[0x5b]	138195	1			T3	4		T4	68		T5	4
valid_sources[0x5c]	172439	1			T3	11		T4	81		T5	5
valid_sources[0x5d]	130094	1			T3	15		T4	90		T5	7
valid_sources[0x5e]	146575	1			T3	23		T4	61		T5	6
valid_sources[0x5f]	136659	1			T3	4		T4	81		T5	6
valid_sources[0x60]	141076	1			T3	1		T4	84		T5	8
valid_sources[0x61]	145959	1			T3	3		T4	63		T5	2
valid_sources[0x62]	140106	1			T3	3		T4	62		T5	4
valid_sources[0x63]	140994	1			T3	7		T4	66		T5	3
valid_sources[0x64]	132521	1			T3	2		T4	55		T5	7
valid_sources[0x65]	146504	1			T2	1		T3	10		T4	78
valid_sources[0x66]	144485	1			T3	2		T4	99		T5	4
valid_sources[0x67]	155298	1			T2	2		T3	8		T4	59
valid_sources[0x68]	141339	1			T3	4		T4	68		T5	4
valid_sources[0x69]	133407	1			T4	81		T5	7		T8	7
valid_sources[0x6a]	132604	1			T2	1		T3	9		T4	73
valid_sources[0x6b]	133485	1			T3	4		T4	79		T5	2
valid_sources[0x6c]	121935	1			T3	6		T4	79		T5	4
valid_sources[0x6d]	136220	1			T3	6		T4	79		T5	9
valid_sources[0x6e]	140500	1			T3	4		T4	77		T8	5
valid_sources[0x6f]	159773	1			T2	2		T3	1		T4	70
valid_sources[0x70]	130687	1			T3	8		T4	81		T5	5
valid_sources[0x71]	157076	1			T3	2		T4	75		T5	5
valid_sources[0x72]	136832	1			T3	21		T4	76		T5	2
valid_sources[0x73]	130546	1			T3	22		T4	65		T5	5
valid_sources[0x74]	131560	1			T3	8		T4	81		T5	4
valid_sources[0x75]	133936	1			T3	3		T4	69		T5	1
valid_sources[0x76]	134859	1			T2	1		T3	4		T4	94
valid_sources[0x77]	136013	1			T2	1		T3	2		T4	83
valid_sources[0x78]	131980	1			T1	12		T3	7		T4	80
valid_sources[0x79]	138937	1			T2	1		T3	6		T4	87
valid_sources[0x7a]	146605	1			T1	3527		T3	6		T4	93
valid_sources[0x7b]	134855	1			T3	5		T4	76		T5	6
valid_sources[0x7c]	137304	1			T3	7		T4	68		T5	7
valid_sources[0x7d]	148536	1			T3	5		T4	58		T5	8
valid_sources[0x7e]	177452	1			T3	1		T4	81		T5	7
valid_sources[0x7f]	137651	1			T3	6		T4	60		T5	8
valid_sources[0x80]	139929	1			T3	12		T4	78		T5	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7242058

1

T1

109

T2

2

T3

271

values[0x0]

all_enables

biggest_size

222129

1

T1

48

T2

15

T3

89

values[0x1]

all_enables

biggest_size

152433

1

T1

29

T2

11

T3

74