Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.48	100.00	100.00	93.91			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	412904454	0	0	0
ctrl_rd_A	412904454	2290	0	0
host_fifo_config_rd_A	412904454	4623	0	0
host_nack_handler_timeout_rd_A	412904454	1584	0	0
host_timeout_ctrl_rd_A	412904454	1521	0	0
intr_enable_rd_A	412904454	3932	0	0
ovrd_rd_A	412904454	2140	0	0
target_fifo_config_rd_A	412904454	1501	0	0
target_id_rd_A	412904454	1902	0	0
target_timeout_ctrl_rd_A	412904454	1577	0	0
timeout_ctrl_rd_A	412904454	1681	0	0
timing0_rd_A	412904454	1620	0	0
timing1_rd_A	412904454	1565	0	0
timing2_rd_A	412904454	1525	0	0
timing3_rd_A	412904454	1743	0	0
timing4_rd_A	412904454	1531	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412904454	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412904454	2290	0	0
T89	12043	150	0	0
T90	15425	340	0	0
T91	1752	14	0	0
T92	5636	28	0	0
T93	6256	33	0	0
T94	6261	27	0	0
T95	1876	9	0	0
T96	3985	41	0	0
T97	10585	14	0	0
T98	11578	168	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412904454	4623	0	0
T39	587962	0	0	0
T99	518723	202	0	0
T100	0	164	0	0
T101	0	464	0	0
T102	0	141	0	0
T103	0	208	0	0
T104	0	172	0	0
T105	0	220	0	0
T106	0	148	0	0
T107	0	249	0	0
T108	0	218	0	0
T109	15787	0	0	0
T110	346104	0	0	0
T111	12282	0	0	0
T112	44646	0	0	0
T113	14576	0	0	0
T114	48840	0	0	0
T115	688406	0	0	0
T116	17234	0	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412904454	1584	0	0
T89	12043	77	0	0
T90	15425	123	0	0
T91	1752	13	0	0
T92	5636	37	0	0
T93	6256	30	0	0
T94	6261	10	0	0
T96	3985	14	0	0
T97	10585	41	0	0
T98	11578	81	0	0
T117	2448	1	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412904454	1521	0	0
T89	12043	25	0	0
T90	15425	55	0	0
T91	1752	8	0	0
T92	5636	68	0	0
T93	6256	73	0	0
T94	6261	40	0	0
T96	3985	64	0	0
T97	10585	25	0	0
T98	11578	55	0	0
T118	3069	14	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412904454	3932	0	0
T17	397590	18	0	0
T18	162242	0	0	0
T23	11517	0	0	0
T33	0	22	0	0
T44	208420	0	0	0
T48	14220	0	0	0
T51	52118	0	0	0
T52	53298	0	0	0
T89	0	249	0	0
T90	0	551	0	0
T101	0	29	0	0
T119	0	27	0	0
T120	0	13	0	0
T121	0	12	0	0
T122	0	16	0	0
T123	0	18	0	0
T124	15349	0	0	0
T125	71474	0	0	0
T126	98855	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412904454	2140	0	0
T17	397590	0	0	0
T23	11517	0	0	0
T43	505179	0	0	0
T44	208420	0	0	0
T46	16773	0	0	0
T86	2118	30	0	0
T124	15349	0	0	0
T127	0	33	0	0
T128	0	74	0	0
T129	0	18	0	0
T130	0	43	0	0
T131	0	13	0	0
T132	0	53	0	0
T133	0	68	0	0
T134	0	42	0	0
T135	0	24	0	0
T136	195749	0	0	0
T137	93361	0	0	0
T138	61612	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412904454	1501	0	0
T89	12043	62	0	0
T90	15425	115	0	0
T91	1752	7	0	0
T92	5636	58	0	0
T93	6256	28	0	0
T94	6261	7	0	0
T95	1876	7	0	0
T96	3985	40	0	0
T97	10585	23	0	0
T98	11578	56	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412904454	1902	0	0
T89	12043	126	0	0
T90	15425	192	0	0
T91	1752	24	0	0
T92	5636	6	0	0
T93	6256	91	0	0
T94	6261	24	0	0
T95	1876	12	0	0
T96	3985	15	0	0
T97	10585	19	0	0
T98	11578	65	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412904454	1577	0	0
T89	12043	67	0	0
T90	15425	136	0	0
T91	1752	10	0	0
T92	5636	49	0	0
T93	6256	76	0	0
T94	6261	26	0	0
T95	1876	7	0	0
T96	3985	4	0	0
T97	10585	16	0	0
T98	11578	74	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412904454	1681	0	0
T89	12043	47	0	0
T90	15425	136	0	0
T91	1752	18	0	0
T92	5636	29	0	0
T93	6256	84	0	0
T94	6261	7	0	0
T95	1876	13	0	0
T96	3985	27	0	0
T97	10585	44	0	0
T98	11578	77	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412904454	1620	0	0
T89	12043	60	0	0
T90	15425	122	0	0
T91	1752	19	0	0
T92	5636	46	0	0
T93	6256	27	0	0
T94	6261	19	0	0
T95	1876	13	0	0
T96	3985	36	0	0
T97	10585	23	0	0
T98	11578	61	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412904454	1565	0	0
T89	12043	36	0	0
T90	15425	101	0	0
T91	1752	14	0	0
T92	5636	44	0	0
T93	6256	22	0	0
T94	6261	23	0	0
T95	1876	13	0	0
T96	3985	33	0	0
T97	10585	44	0	0
T98	11578	49	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412904454	1525	0	0
T89	12043	74	0	0
T90	15425	138	0	0
T91	1752	15	0	0
T92	5636	22	0	0
T93	6256	42	0	0
T94	6261	2	0	0
T95	1876	3	0	0
T96	3985	46	0	0
T97	10585	22	0	0
T98	11578	50	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412904454	1743	0	0
T89	12043	65	0	0
T90	15425	110	0	0
T91	1752	5	0	0
T92	5636	15	0	0
T93	6256	93	0	0
T94	6261	18	0	0
T95	1876	19	0	0
T96	3985	31	0	0
T97	10585	18	0	0
T98	11578	95	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412904454	1531	0	0
T89	12043	67	0	0
T90	15425	140	0	0
T91	1752	20	0	0
T92	5636	52	0	0
T93	6256	25	0	0
T94	6261	23	0	0
T95	1876	1	0	0
T96	3985	13	0	0
T97	10585	46	0	0
T98	11578	90	0	0