Module Definition
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Module : i2c_controller_fsm
SCORELINECONDTOGGLEFSMBRANCHASSERT
83.63 90.34 75.91 66.67 85.25 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.i2c_core.u_i2c_controller_fsm 83.63 90.34 75.91 66.67 85.25 100.00



Module Instance : tb.dut.i2c_core.u_i2c_controller_fsm

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
83.63 90.34 75.91 66.67 85.25 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
83.63 90.34 75.91 66.67 85.25 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.58 97.74 79.23 93.33 100.00 i2c_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : i2c_controller_fsm
Line No.TotalCoveredPercent
TOTAL43539390.34
ALWAYS1211515100.00
ALWAYS14633100.00
ALWAYS15955100.00
CONT_ASSIGN18211100.00
ALWAYS18666100.00
ALWAYS2029888.89
CONT_ASSIGN21711100.00
ALWAYS22177100.00
ALWAYS23466100.00
ALWAYS24555100.00
ALWAYS25277100.00
ALWAYS26555100.00
CONT_ASSIGN27611100.00
ALWAYS28488100.00
ALWAYS2968787.50
ALWAYS30833100.00
CONT_ASSIGN34111100.00
ALWAYS34614713994.56
ALWAYS60219115983.25
ALWAYS96133100.00
CONT_ASSIGN96811100.00
CONT_ASSIGN96911100.00
CONT_ASSIGN97211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
121 1 1
122 1 1
123 1 1
124 1 1
125 1 1
126 1 1
127 1 1
128 1 1
129 1 1
130 1 1
131 1 1
132 1 1
133 1 1
136 1 1
141 1 1
MISSING_ELSE
146 1 1
147 1 1
149 1 1
159 1 1
160 1 1
161 1 1
163 1 1
165 1 1
182 1 1
186 1 1
187 1 1
189 1 1
190 1 1
191 1 1
192 1 1
MISSING_ELSE
202 1 1
203 1 1
204 1 1
205 1 1
207 1 1
208 1 1
209 0 1
MISSING_ELSE
212 1 1
213 1 1
217 1 1
221 1 1
222 1 1
223 1 1
224 1 1
225 1 1
226 1 1
228 1 1
234 1 1
235 1 1
236 1 1
237 1 1
238 1 1
239 1 1
MISSING_ELSE
245 2 2
246 2 2
247 1 1
252 1 1
253 1 1
254 1 1
255 1 1
256 1 1
257 1 1
259 1 1
265 1 1
266 1 1
267 1 1
269 1 1
270 1 1
276 1 1
284 1 1
285 1 1
286 1 1
287 1 1
288 1 1
289 1 1
290 1 1
291 1 1
MISSING_ELSE
296 1 1
297 1 1
298 1 1
299 0 1
300 1 1
301 1 1
302 1 1
303 1 1
MISSING_ELSE
308 1 1
309 1 1
311 1 1
341 1 1
346 1 1
347 1 1
348 1 1
349 1 1
350 1 1
351 1 1
352 1 1
353 1 1
354 1 1
355 1 1
356 1 1
357 1 1
358 1 1
359 1 1
360 1 1
361 1 1
366 1 1
367 1 1
368 1 1
369 1 1
371 1 1
372 1 1
382 1 1
383 1 1
384 1 1
385 1 1
387 1 1
388 1 1
392 0 1
393 1 1
394 1 1
395 1 1
MISSING_ELSE
400 1 1
401 1 1
402 1 1
403 1 1
404 1 2
MISSING_ELSE
408 1 1
409 1 1
410 1 1
411 1 1
414 1 1
415 1 1
416 1 1
418 1 1
420 1 1
421 1 1
425 1 1
426 1 1
427 1 1
428 1 1
429 1 1
430 1 2
MISSING_ELSE
431 1 1
433 1 1
MISSING_ELSE
438 1 1
439 1 1
440 1 1
441 1 1
445 1 1
446 1 1
447 1 1
451 1 1
452 1 1
453 1 1
454 2 2
MISSING_ELSE
455 1 1
456 2 2
MISSING_ELSE
457 1 1
459 1 1
MISSING_ELSE
464 1 1
465 1 1
466 1 1
470 1 1
471 1 1
472 1 1
476 1 1
477 1 1
478 1 1
479 1 2
MISSING_ELSE
480 1 1
482 1 1
MISSING_ELSE
487 1 1
488 1 1
489 1 1
490 1 1
491 1 1
MISSING_ELSE
496 1 1
497 1 1
498 1 1
502 2 2
503 2 2
504 1 1
508 1 1
509 2 2
510 2 2
511 1 1
512 1 1
513 1 1
514 1 1
515 1 2
MISSING_ELSE
516 1 1
518 0 1
MISSING_ELSE
523 1 1
524 2 2
525 2 2
526 1 1
527 1 1
528 1 1
532 1 1
533 1 1
534 1 1
535 1 1
539 1 1
540 1 1
541 1 1
542 1 1
543 1 1
544 1 1
546 0 1
MISSING_ELSE
551 1 1
552 1 1
553 1 1
554 1 1
555 1 1
557 0 1
558 1 1
559 1 1
MISSING_ELSE
564 1 1
570 1 1
574 1 1
575 2 2
576 1 1
577 1 1
602 1 1
603 1 1
604 1 1
605 1 1
606 1 1
607 1 1
608 1 1
609 1 1
610 1 1
611 1 1
612 1 1
614 1 1
618 1 1
619 1 1
632 1 1
634 0 1
635 0 1
636 0 1
637 0 1
MISSING_ELSE
639 1 1
640 1 1
641 1 1
MISSING_ELSE
MISSING_ELSE
644 1 1
645 0 1
646 0 1
647 0 1
648 0 1
MISSING_ELSE
658 1 1
661 0 1
662 1 1
664 0 1
665 0 1
667 0 1
668 1 1
670 0 1
671 1 1
672 1 1
673 1 1
674 1 1
MISSING_ELSE
679 1 1
680 1 1
681 1 1
682 1 1
MISSING_ELSE
687 1 1
688 1 1
689 1 1
690 1 1
MISSING_ELSE
695 1 1
696 1 1
697 1 1
698 1 1
699 1 1
701 1 1
702 1 1
MISSING_ELSE
708 1 1
710 0 1
711 0 1
712 1 1
714 1 1
715 1 1
718 1 1
719 1 1
720 1 1
MISSING_ELSE
725 1 1
726 1 1
727 1 1
728 1 1
729 1 1
730 1 1
732 1 1
733 1 1
MISSING_ELSE
740 1 1
741 1 1
742 1 1
743 1 1
MISSING_ELSE
748 1 1
750 1 1
751 1 1
752 1 1
754 1 1
756 1 1
757 1 1
758 1 1
759 1 1
MISSING_ELSE
765 1 1
766 1 1
767 1 1
768 1 1
769 1 1
771 1 1
772 1 1
773 1 1
MISSING_ELSE
779 1 1
780 1 1
781 1 1
782 1 1
MISSING_ELSE
787 1 1
789 0 1
790 0 1
791 1 1
793 1 1
794 1 1
795 1 1
796 1 1
797 1 1
798 1 1
MISSING_ELSE
803 1 1
804 1 1
805 1 1
806 1 1
807 1 1
808 1 1
809 1 1
811 1 1
812 1 1
MISSING_ELSE
819 1 1
820 1 1
821 1 1
822 1 1
MISSING_ELSE
827 1 1
829 0 1
830 0 1
831 1 1
833 0 1
834 1 1
835 1 1
836 1 1
837 1 1
MISSING_ELSE
842 1 1
843 1 1
844 1 1
845 1 1
846 1 1
847 1 1
849 1 1
850 1 1
851 1 1
854 1 1
855 1 1
856 1 1
857 1 1
MISSING_ELSE
863 1 1
864 1 1
865 1 1
866 1 1
MISSING_ELSE
871 1 1
873 0 1
874 0 1
875 1 1
877 0 1
878 1 1
879 1 1
MISSING_ELSE
884 1 1
886 0 1
887 0 1
888 1 1
889 1 1
890 1 1
892 0 1
893 0 1
894 0 1
896 1 1
897 1 1
898 1 1
MISSING_ELSE
904 1 1
905 1 1
906 1 1
907 1 1
908 1 1
909 1 1
910 1 1
911 1 1
912 1 1
914 1 1
915 1 1
916 1 1
917 1 1
922 1 1
923 0 1
924 0 1
925 0 1
926 0 1
927 1 1
929 1 1
930 1 1
931 1 1
933 1 1
934 1 1
935 1 1
954 1 1
955 1 1
MISSING_ELSE
961 1 1
962 1 1
964 1 1
968 1 1
969 1 1
972 1 1


Cond Coverage for Module : i2c_controller_fsm
TotalCoveredPercent
Conditions27420875.91
Logical27420875.91
Non-Logical00
Event00

 LINE       136
 EXPRESSION (host_enable_i || (((!host_idle_o)) && ((!host_enable_i))))
             ------1------    --------------------2-------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT11,T12,T13
10CoveredT4,T14,T15

 LINE       136
 SUB-EXPRESSION (((!host_idle_o)) && ((!host_enable_i)))
                 --------1-------    ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T14,T15
11CoveredT11,T12,T13

 LINE       161
 EXPRESSION (stretch_en && ((!scl_i)))
             -----1----    -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T14,T15
11CoveredT4,T14,T15

 LINE       189
 EXPRESSION (stretch_idle_cnt == stretch_cnt_threshold)
            ---------------------1---------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T14,T15

 LINE       246
 EXPRESSION (fmt_byte_i == '0)
            ---------1--------
-1-StatusTests
0CoveredT4,T14,T16
1CoveredT17,T18,T19

 LINE       276
 EXPRESSION (event_sda_unstable_o || sda_interference_i || ctrl_symbol_failed)
             ----------1---------    ---------2--------    ---------3--------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001Not Covered
010CoveredT20,T21,T22
100CoveredT23,T24,T20

 LINE       286
 EXPRESSION (trans_started && (((!host_enable_i)) || event_arbitration_lost_o))
             ------1------    ------------------------2-----------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T14,T15
11CoveredT23,T24,T11

 LINE       286
 SUB-EXPRESSION (((!host_enable_i)) || event_arbitration_lost_o)
                 ---------1--------    ------------2-----------
-1--2-StatusTests
00CoveredT4,T14,T15
01CoveredT23,T24,T20
10CoveredT1,T2,T3

 LINE       298
 EXPRESSION (pend_restart && ((!host_enable_i)))
             ------1-----    ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT15,T25,T17
11Not Covered

 LINE       341
 EXPRESSION (unhandled_unexp_nak_i && host_enable_i && (state_q == Idle) && host_nack_handler_timeout_en_i && ((!unhandled_nak_timeout_i)))
             ----------1----------    ------2------    --------3--------    ---------------4--------------    --------------5-------------
-1--2--3--4--5-StatusTests
01111CoveredT26,T27,T28
10111Not Covered
11011CoveredT26,T27,T28
11101Not Covered
11110Not Covered
11111CoveredT26,T27,T28

 LINE       341
 SUB-EXPRESSION (state_q == Idle)
                --------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       388
 EXPRESSION (trans_started && ((!scl_i)) && scl_i_q)
             ------1------    -----2----    ---3---
-1--2--3-StatusTests
011Not Covered
101CoveredT15,T25,T17
110CoveredT15,T25,T17
111Not Covered

 LINE       393
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------
-1-StatusTests
0CoveredT4,T14,T15
1CoveredT4,T14,T15

 LINE       404
 EXPRESSION (scl_i_q && ((!scl_i)))
             ---1---    -----2----
-1--2-StatusTests
01CoveredT15,T26,T29
10CoveredT4,T14,T15
11Not Covered

 LINE       430
 EXPRESSION (scl_i_q && ((!scl_i)))
             ---1---    -----2----
-1--2-StatusTests
01CoveredT4,T14,T15
10CoveredT4,T14,T15
11Not Covered

 LINE       431
 EXPRESSION (scl_i_q && scl_i && (sda_i_q != sda_i))
             ---1---    --2--    ---------3--------
-1--2--3-StatusTests
011CoveredT20,T30,T31
101Not Covered
110CoveredT4,T14,T15
111CoveredT23,T24,T20

 LINE       431
 SUB-EXPRESSION (sda_i_q != sda_i)
                ---------1--------
-1-StatusTests
0CoveredT4,T14,T15
1CoveredT23,T24,T32

 LINE       454
 EXPRESSION (((!scl_i_q)) && scl_i && sda_i && ((!fmt_flag_nak_ok_i)))
             ------1-----    --2--    --3--    -----------4----------
-1--2--3--4-StatusTests
0111CoveredT23,T24,T26
1011CoveredT4,T14,T15
1101CoveredT4,T14,T15
1110CoveredT26,T27,T28
1111CoveredT26,T27,T28

 LINE       456
 EXPRESSION (scl_i_q && ((!scl_i)))
             ---1---    -----2----
-1--2-StatusTests
01CoveredT4,T14,T15
10CoveredT4,T14,T15
11CoveredT23,T24,T20

 LINE       457
 EXPRESSION (scl_i_q && scl_i && (sda_i_q != sda_i))
             ---1---    --2--    ---------3--------
-1--2--3-StatusTests
011Not Covered
101CoveredT23,T20,T21
110CoveredT4,T14,T15
111CoveredT23,T24,T20

 LINE       457
 SUB-EXPRESSION (sda_i_q != sda_i)
                ---------1--------
-1-StatusTests
0CoveredT4,T14,T15
1CoveredT4,T14,T15

 LINE       479
 EXPRESSION (scl_i_q && ((!scl_i)))
             ---1---    -----2----
-1--2-StatusTests
01CoveredT4,T14,T16
10CoveredT4,T14,T16
11Not Covered

 LINE       480
 EXPRESSION (scl_i_q && scl_i && (sda_i_q != sda_i))
             ---1---    --2--    ---------3--------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110CoveredT4,T14,T16
111CoveredT33,T34

 LINE       480
 SUB-EXPRESSION (sda_i_q != sda_i)
                ---------1--------
-1-StatusTests
0CoveredT4,T14,T16
1CoveredT4,T16,T35

 LINE       489
 EXPRESSION ((bit_index == '0) && (tcount_q == 16'b1))
             --------1--------    ---------2---------
-1--2-StatusTests
01CoveredT4,T14,T16
10CoveredT4,T14,T16
11CoveredT4,T14,T16

 LINE       489
 SUB-EXPRESSION (bit_index == '0)
                --------1--------
-1-StatusTests
0CoveredT4,T14,T16
1CoveredT4,T14,T16

 LINE       489
 SUB-EXPRESSION (tcount_q == 16'b1)
                ---------1---------
-1-StatusTests
0CoveredT4,T14,T16
1CoveredT4,T14,T16

 LINE       503
 EXPRESSION (byte_index == 9'b1)
            ----------1---------
-1-StatusTests
0CoveredT4,T14,T16
1CoveredT4,T14,T16

 LINE       510
 EXPRESSION (byte_index == 9'b1)
            ----------1---------
-1-StatusTests
0CoveredT4,T14,T16
1CoveredT4,T14,T16

 LINE       515
 EXPRESSION (scl_i_q && ((!scl_i)))
             ---1---    -----2----
-1--2-StatusTests
01CoveredT4,T14,T16
10CoveredT4,T14,T16
11Not Covered

 LINE       516
 EXPRESSION (scl_i_q && scl_i && (sda_i_q != sda_i))
             ---1---    --2--    ---------3--------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110CoveredT4,T14,T16
111Not Covered

 LINE       516
 SUB-EXPRESSION (sda_i_q != sda_i)
                ---------1--------
-1-StatusTests
0CoveredT4,T14,T16
1CoveredT27,T33,T31

 LINE       525
 EXPRESSION (byte_index == 9'b1)
            ----------1---------
-1-StatusTests
0CoveredT4,T14,T16
1CoveredT4,T14,T16

 LINE       544
 EXPRESSION (((!scl_i)) && scl_i_q)
             -----1----    ---2---
-1--2-StatusTests
01CoveredT4,T14,T15
10CoveredT4,T14,T15
11Not Covered

 LINE       555
 EXPRESSION (((!sda_i)) && ((!scl_i)))
             -----1----    -----2----
-1--2-StatusTests
01Not Covered
10CoveredT4,T14,T15
11Not Covered

 LINE       570
 EXPRESSION (fmt_flag_start_before_i && ((!trans_started)))
             -----------1-----------    ---------2--------
-1--2-StatusTests
01CoveredT36,T37,T38
10CoveredT15,T25,T17
11CoveredT4,T14,T15

 LINE       619
 EXPRESSION (unhandled_unexp_nak_i || unhandled_nak_timeout_i || halt_controller_i)
             ----------1----------    -----------2-----------    --------3--------
-1--2--3-StatusTests
000CoveredT4,T14,T15
001CoveredT23,T24,T20
010Not Covered
100Not Covered

 LINE       632
 EXPRESSION (trans_started && unhandled_nak_cnt_expired)
             ------1------    ------------2------------
-1--2-StatusTests
01Not Covered
10CoveredT26,T27,T28
11Not Covered

 LINE       640
 EXPRESSION (trans_started || bus_free_i)
             ------1------    -----2----
-1--2-StatusTests
00CoveredT39,T40,T41
01CoveredT4,T14,T15
10Not Covered

 LINE       644
 EXPRESSION (trans_started && ((!host_enable_i)))
             ------1------    ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       658
 EXPRESSION (((!trans_started)) && ((!scl_i)))
             ---------1--------    -----2----
-1--2-StatusTests
01CoveredT15,T25,T17
10CoveredT4,T14,T15
11Not Covered

 LINE       662
 EXPRESSION (trans_started && ((!scl_i)) && ((!scl_i_q)) && stretch_predict_cnt_expired)
             ------1------    -----2----    ------3-----    -------------4-------------
-1--2--3--4-StatusTests
0111Not Covered
1011CoveredT25,T42,T27
1101Not Covered
1110CoveredT15,T25,T17
1111Not Covered

 LINE       668
 EXPRESSION (trans_started && ((!scl_i)) && scl_i_q)
             ------1------    -----2----    ---3---
-1--2--3-StatusTests
011Not Covered
101CoveredT15,T25,T17
110CoveredT15,T25,T17
111Not Covered

 LINE       671
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------
-1-StatusTests
0CoveredT4,T14,T15
1CoveredT4,T14,T15

 LINE       679
 EXPRESSION ((tcount_q == 16'b1) || (((!scl_i)) && scl_i_q))
             ---------1---------    -----------2-----------
-1--2-StatusTests
00CoveredT4,T14,T15
01Not Covered
10CoveredT4,T14,T15

 LINE       679
 SUB-EXPRESSION (tcount_q == 16'b1)
                ---------1---------
-1-StatusTests
0CoveredT4,T14,T15
1CoveredT4,T14,T15

 LINE       679
 SUB-EXPRESSION (((!scl_i)) && scl_i_q)
                 -----1----    ---2---
-1--2-StatusTests
01CoveredT4,T14,T15
10CoveredT15,T26,T29
11Not Covered

 LINE       687
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------
-1-StatusTests
0CoveredT4,T15,T16
1CoveredT4,T14,T15

 LINE       695
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------
-1-StatusTests
0CoveredT4,T14,T15
1CoveredT4,T14,T15

 LINE       708
 EXPRESSION (((!scl_i)) && ((!scl_i_q)) && stretch_predict_cnt_expired)
             -----1----    ------2-----    -------------3-------------
-1--2--3-StatusTests
011CoveredT4,T15,T16
101Not Covered
110CoveredT4,T14,T15
111Not Covered

 LINE       712
 EXPRESSION (scl_i_q && scl_i && (sda_i_q != sda_i))
             ---1---    --2--    ---------3--------
-1--2--3-StatusTests
011CoveredT20,T30,T31
101Not Covered
110CoveredT4,T14,T15
111CoveredT23,T24,T20

 LINE       712
 SUB-EXPRESSION (sda_i_q != sda_i)
                ---------1--------
-1-StatusTests
0CoveredT4,T14,T15
1CoveredT23,T24,T32

 LINE       715
 EXPRESSION ((tcount_q == 16'b1) || (((!scl_i)) && scl_i_q))
             ---------1---------    -----------2-----------
-1--2-StatusTests
00CoveredT4,T14,T15
01Not Covered
10CoveredT4,T14,T15

 LINE       715
 SUB-EXPRESSION (tcount_q == 16'b1)
                ---------1---------
-1-StatusTests
0CoveredT4,T14,T15
1CoveredT4,T14,T15

 LINE       715
 SUB-EXPRESSION (((!scl_i)) && scl_i_q)
                 -----1----    ---2---
-1--2-StatusTests
01CoveredT4,T14,T15
10CoveredT4,T14,T15
11Not Covered

 LINE       725
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------
-1-StatusTests
0CoveredT4,T14,T15
1CoveredT4,T14,T15

 LINE       728
 EXPRESSION (bit_index == '0)
            --------1--------
-1-StatusTests
0CoveredT4,T14,T15
1CoveredT4,T14,T15

 LINE       740
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------
-1-StatusTests
0CoveredT4,T14,T15
1CoveredT4,T14,T15

 LINE       748
 EXPRESSION (((!scl_i)) && ((!scl_i_q)) && stretch_predict_cnt_expired)
             -----1----    ------2-----    -------------3-------------
-1--2--3-StatusTests
011CoveredT4,T14,T15
101CoveredT23,T24,T20
110CoveredT4,T14,T15
111CoveredT4,T14,T15

 LINE       752
 EXPRESSION (scl_i_q && scl_i && (sda_i_q != sda_i))
             ---1---    --2--    ---------3--------
-1--2--3-StatusTests
011Not Covered
101CoveredT23,T20,T21
110CoveredT4,T14,T15
111CoveredT23,T24,T20

 LINE       752
 SUB-EXPRESSION (sda_i_q != sda_i)
                ---------1--------
-1-StatusTests
0CoveredT4,T14,T15
1CoveredT4,T15,T16

 LINE       756
 EXPRESSION ((tcount_q == 16'b1) || (((!scl_i)) && scl_i_q))
             ---------1---------    -----------2-----------
-1--2-StatusTests
00CoveredT4,T14,T15
01CoveredT23,T24,T21
10CoveredT4,T14,T15

 LINE       756
 SUB-EXPRESSION (tcount_q == 16'b1)
                ---------1---------
-1-StatusTests
0CoveredT4,T14,T15
1CoveredT4,T14,T15

 LINE       756
 SUB-EXPRESSION (((!scl_i)) && scl_i_q)
                 -----1----    ---2---
-1--2-StatusTests
01CoveredT4,T14,T15
10CoveredT4,T14,T15
11CoveredT23,T24,T20

 LINE       765
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------
-1-StatusTests
0CoveredT4,T14,T15
1CoveredT4,T14,T15

 LINE       779
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------
-1-StatusTests
0CoveredT4,T14,T16
1CoveredT4,T14,T16

 LINE       787
 EXPRESSION (((!scl_i)) && ((!scl_i_q)) && stretch_predict_cnt_expired)
             -----1----    ------2-----    -------------3-------------
-1--2--3-StatusTests
011CoveredT4,T16,T35
101Not Covered
110CoveredT4,T14,T16
111Not Covered

 LINE       791
 EXPRESSION (scl_i_q && scl_i && (sda_i_q != sda_i))
             ---1---    --2--    ---------3--------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110CoveredT4,T14,T16
111CoveredT33,T34

 LINE       791
 SUB-EXPRESSION (sda_i_q != sda_i)
                ---------1--------
-1-StatusTests
0CoveredT4,T14,T16
1CoveredT4,T16,T35

 LINE       794
 EXPRESSION ((tcount_q == 16'b1) || (((!scl_i)) && scl_i_q))
             ---------1---------    -----------2-----------
-1--2-StatusTests
00CoveredT4,T14,T16
01Not Covered
10CoveredT4,T14,T16

 LINE       794
 SUB-EXPRESSION (tcount_q == 16'b1)
                ---------1---------
-1-StatusTests
0CoveredT4,T14,T16
1CoveredT4,T14,T16

 LINE       794
 SUB-EXPRESSION (((!scl_i)) && scl_i_q)
                 -----1----    ---2---
-1--2-StatusTests
01CoveredT4,T14,T16
10CoveredT4,T14,T16
11Not Covered

 LINE       803
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------
-1-StatusTests
0CoveredT4,T14,T16
1CoveredT4,T14,T16

 LINE       806
 EXPRESSION (bit_index == '0)
            --------1--------
-1-StatusTests
0CoveredT4,T14,T16
1CoveredT4,T14,T16

 LINE       819
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------
-1-StatusTests
0CoveredT4,T14,T16
1CoveredT4,T14,T16

 LINE       827
 EXPRESSION (((!scl_i)) && ((!scl_i_q)) && stretch_predict_cnt_expired)
             -----1----    ------2-----    -------------3-------------
-1--2--3-StatusTests
011CoveredT4,T16,T35
101Not Covered
110CoveredT4,T14,T16
111Not Covered

 LINE       831
 EXPRESSION (scl_i_q && scl_i && (sda_i_q != sda_i))
             ---1---    --2--    ---------3--------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110CoveredT4,T14,T16
111Not Covered

 LINE       831
 SUB-EXPRESSION (sda_i_q != sda_i)
                ---------1--------
-1-StatusTests
0CoveredT4,T14,T16
1CoveredT27,T33,T31

 LINE       834
 EXPRESSION ((tcount_q == 16'b1) || (((!scl_i)) && scl_i_q))
             ---------1---------    -----------2-----------
-1--2-StatusTests
00CoveredT4,T14,T16
01Not Covered
10CoveredT4,T14,T16

 LINE       834
 SUB-EXPRESSION (tcount_q == 16'b1)
                ---------1---------
-1-StatusTests
0CoveredT4,T14,T16
1CoveredT4,T14,T16

 LINE       834
 SUB-EXPRESSION (((!scl_i)) && scl_i_q)
                 -----1----    ---2---
-1--2-StatusTests
01CoveredT4,T14,T16
10CoveredT4,T14,T16
11Not Covered

 LINE       842
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------
-1-StatusTests
0CoveredT4,T14,T16
1CoveredT4,T14,T16

 LINE       843
 EXPRESSION (byte_index == 9'b1)
            ----------1---------
-1-StatusTests
0CoveredT4,T14,T16
1CoveredT4,T14,T16

 LINE       863
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------
-1-StatusTests
0CoveredT4,T14,T15
1CoveredT4,T14,T15

 LINE       871
 EXPRESSION (((!scl_i)) && ((!scl_i_q)) && stretch_predict_cnt_expired)
             -----1----    ------2-----    -------------3-------------
-1--2--3-StatusTests
011CoveredT4,T15,T16
101Not Covered
110CoveredT4,T14,T15
111Not Covered

 LINE       875
 EXPRESSION (((!scl_i)) && scl_i_q)
             -----1----    ---2---
-1--2-StatusTests
01CoveredT4,T14,T15
10CoveredT4,T14,T15
11Not Covered

 LINE       878
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------
-1-StatusTests
0CoveredT4,T14,T15
1CoveredT4,T14,T15

 LINE       884
 EXPRESSION (((!sda_i)) && ((!scl_i)))
             -----1----    -----2----
-1--2-StatusTests
01Not Covered
10CoveredT4,T14,T15
11Not Covered

 LINE       909
 EXPRESSION (fmt_flag_start_before_i && ((!trans_started)))
             -----------1-----------    ---------2--------
-1--2-StatusTests
01CoveredT36,T37,T38
10CoveredT15,T25,T17
11CoveredT4,T14,T15

 LINE       922
 EXPRESSION (((!host_enable_i)) && trans_started)
             ---------1--------    ------2------
-1--2-StatusTests
01CoveredT4,T14,T15
10CoveredT11,T12,T13
11Not Covered

 LINE       927
 EXPRESSION (((!host_enable_i)) || (fmt_fifo_depth_i == 7'b1) || unhandled_unexp_nak_i || ((!trans_started)))
             ---------1--------    -------------2------------    ----------3----------    ---------4--------
-1--2--3--4-StatusTests
0000CoveredT4,T14,T15
0001Not Covered
0010CoveredT26,T27,T28
0100Not Covered
1000Not Covered

 LINE       927
 SUB-EXPRESSION (fmt_fifo_depth_i == 7'b1)
                -------------1------------
-1-StatusTests
0CoveredT4,T14,T15
1CoveredT4,T14,T15

 LINE       954
 EXPRESSION (trans_started && (sda_interference_i || ctrl_symbol_failed))
             ------1------    ---------------------2--------------------
-1--2-StatusTests
01Not Covered
10CoveredT4,T14,T15
11CoveredT20,T21,T22

 LINE       954
 SUB-EXPRESSION (sda_interference_i || ctrl_symbol_failed)
                 ---------1--------    ---------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT20,T21,T22

 LINE       972
 EXPRESSION (stretch_en && timeout_enable_i && (stretch_idle_cnt > 31'(stretch_timeout_i)))
             -----1----    --------2-------    ---------------------3---------------------
-1--2--3-StatusTests
011CoveredT16,T43,T44
101CoveredT15,T16,T45
110CoveredT4,T14,T15
111CoveredT4,T14,T15

FSM Coverage for Module : i2c_controller_fsm
Summary for FSM :: state_q
TotalCoveredPercent
States 21 21 100.00 (Not included in score)
Transitions 51 34 66.67
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
Active 641 Covered T4,T14,T15
ClockLow 688 Covered T4,T14,T15
ClockLowAck 729 Covered T4,T14,T15
ClockPulse 701 Covered T4,T14,T15
ClockPulseAck 741 Covered T4,T14,T15
ClockStart 680 Covered T4,T14,T15
ClockStop 635 Covered T4,T14,T15
HoldBit 718 Covered T4,T14,T15
HoldDevAck 757 Covered T4,T14,T15
HoldStart 672 Covered T4,T14,T15
HoldStop 879 Covered T4,T14,T15
HostClockLowAck 807 Covered T4,T14,T16
HostClockPulseAck 820 Covered T4,T14,T16
HostHoldBitAck 835 Covered T4,T14,T16
Idle 661 Covered T1,T2,T3
PopFmtFifo 771 Covered T4,T14,T15
ReadClockLow 811 Covered T4,T14,T16
ReadClockPulse 780 Covered T4,T14,T16
ReadHoldBit 795 Covered T4,T14,T16
SetupStart 664 Covered T4,T14,T15
SetupStop 864 Covered T4,T14,T15


transitionsLine No.CoveredTests
Active->ClockLow 914 Covered T4,T15,T35
Active->Idle 955 Not Covered
Active->ReadClockLow 906 Covered T4,T14,T16
Active->SetupStart 910 Covered T4,T14,T15
ClockLow->ClockPulse 701 Covered T4,T14,T15
ClockLow->Idle 955 Not Covered
ClockLow->SetupStart 698 Covered T15,T25,T17
ClockLowAck->ClockPulseAck 741 Covered T4,T14,T15
ClockLowAck->Idle 955 Not Covered
ClockPulse->HoldBit 718 Covered T4,T14,T15
ClockPulse->Idle 714 Covered T23,T24,T20
ClockPulseAck->HoldDevAck 757 Covered T4,T14,T15
ClockPulseAck->Idle 754 Covered T23,T24,T20
ClockStart->ClockLow 688 Covered T4,T14,T15
ClockStart->Idle 955 Not Covered
ClockStop->Idle 955 Not Covered
ClockStop->SetupStop 864 Covered T4,T14,T15
HoldBit->ClockLow 732 Covered T4,T14,T15
HoldBit->ClockLowAck 729 Covered T4,T14,T15
HoldBit->Idle 955 Not Covered
HoldDevAck->ClockStop 767 Covered T4,T15,T35
HoldDevAck->Idle 955 Covered T23,T24,T20
HoldDevAck->PopFmtFifo 771 Covered T4,T14,T15
HoldStart->ClockStart 680 Covered T4,T14,T15
HoldStart->Idle 955 Not Covered
HoldStop->Idle 886 Not Covered
HoldStop->PopFmtFifo 896 Covered T4,T14,T15
HostClockLowAck->HostClockPulseAck 820 Covered T4,T14,T16
HostClockLowAck->Idle 955 Not Covered
HostClockPulseAck->HostHoldBitAck 835 Covered T4,T14,T16
HostClockPulseAck->Idle 833 Not Covered
HostHoldBitAck->ClockStop 845 Covered T4,T14,T16
HostHoldBitAck->Idle 955 Not Covered
HostHoldBitAck->PopFmtFifo 849 Covered T17,T44,T23
HostHoldBitAck->ReadClockLow 854 Covered T4,T14,T16
Idle->Active 641 Covered T4,T14,T15
Idle->ClockStop 635 Not Covered
PopFmtFifo->Active 933 Covered T4,T14,T15
PopFmtFifo->ClockStop 924 Not Covered
PopFmtFifo->Idle 929 Covered T4,T14,T15
ReadClockLow->Idle 955 Not Covered
ReadClockLow->ReadClockPulse 780 Covered T4,T14,T16
ReadClockPulse->Idle 793 Covered T33,T34
ReadClockPulse->ReadHoldBit 795 Covered T4,T14,T16
ReadHoldBit->HostClockLowAck 807 Covered T4,T14,T16
ReadHoldBit->Idle 955 Not Covered
ReadHoldBit->ReadClockLow 811 Covered T4,T14,T16
SetupStart->HoldStart 672 Covered T4,T14,T15
SetupStart->Idle 661 Not Covered
SetupStop->HoldStop 879 Covered T4,T14,T15
SetupStop->Idle 877 Not Covered



Branch Coverage for Module : i2c_controller_fsm
Line No.TotalCoveredPercent
Branches 183 156 85.25
IF 122 13 12 92.31
IF 146 2 2 100.00
IF 159 3 3 100.00
IF 186 4 4 100.00
IF 202 4 3 75.00
IF 221 4 4 100.00
IF 234 4 4 100.00
IF 245 3 3 100.00
IF 252 4 4 100.00
IF 265 2 2 100.00
IF 284 5 5 100.00
IF 296 5 4 80.00
IF 308 2 2 100.00
CASE 361 53 44 83.02
CASE 614 71 56 78.87
IF 954 2 2 100.00
IF 961 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 122 if (load_tcount) -2-: 123 case (tcount_sel) -3-: 136 if ((host_enable_i || ((!host_idle_o) && (!host_enable_i))))

Branches:
-1--2--3-StatusTests
1 tSetupStart - Covered T4,T14,T15
1 tHoldStart - Covered T4,T14,T15
1 tClockStart - Covered T4,T14,T15
1 tClockLow - Covered T4,T14,T15
1 tClockPulse - Covered T4,T14,T15
1 tClockHigh - Covered T4,T14,T15
1 tHoldBit - Covered T4,T14,T15
1 tClockStop - Covered T4,T14,T15
1 tSetupStop - Covered T4,T14,T15
1 tNoDelay - Covered T4,T14,T15
1 default - Not Covered
0 - 1 Covered T4,T14,T15
0 - 0 Covered T1,T2,T3


LineNo. Expression -1-: 146 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 159 if ((!rst_ni)) -2-: 161 if ((stretch_en && (!scl_i)))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T4,T14,T15
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 186 if ((!rst_ni)) -2-: 189 if ((stretch_idle_cnt == stretch_cnt_threshold)) -3-: 191 if ((!stretch_en))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T4,T14,T15
0 0 1 Covered T1,T2,T3
0 0 0 Covered T4,T14,T15


LineNo. Expression -1-: 202 if ((!rst_ni)) -2-: 205 if (incr_nak_cnt) -3-: 208 if ((unhandled_nak_cnt > host_nack_handler_timeout_i))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 1 Not Covered
0 1 0 Covered T26,T27,T28
0 0 - Covered T1,T2,T3


LineNo. Expression -1-: 221 if ((!rst_ni)) -2-: 223 if (bit_clr) -3-: 225 if (bit_decr)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T4,T14,T15
0 0 1 Covered T4,T14,T15
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 234 if ((!rst_ni)) -2-: 236 if (read_byte_clr) -3-: 238 if (shift_data_en)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T4,T14,T16
0 0 1 Covered T4,T14,T16
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 245 if ((!fmt_flag_read_bytes_i)) -2-: 246 if ((fmt_byte_i == '0))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T17,T18,T19
0 0 Covered T4,T14,T16


LineNo. Expression -1-: 252 if ((!rst_ni)) -2-: 254 if (byte_clr) -3-: 256 if (byte_decr)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T4,T14,T16
0 0 1 Covered T4,T14,T16
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 265 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 284 if ((!rst_ni)) -2-: 286 if ((trans_started && ((!host_enable_i) || event_arbitration_lost_o))) -3-: 288 if (log_start) -4-: 290 if (log_stop)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T23,T24,T11
0 0 1 - Covered T4,T14,T15
0 0 0 1 Covered T4,T14,T15
0 0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 296 if ((!rst_ni)) -2-: 298 if ((pend_restart && (!host_enable_i))) -3-: 300 if (req_restart) -4-: 302 if (log_start)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Not Covered
0 0 1 - Covered T15,T25,T17
0 0 0 1 Covered T4,T14,T15
0 0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 308 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 361 case (state_q) -2-: 367 if (trans_started) -3-: 388 if (((trans_started && (!scl_i)) && scl_i_q)) -4-: 393 if ((tcount_q == 16'b1)) -5-: 404 if ((scl_i_q && (!scl_i))) -6-: 415 if (pend_restart) -7-: 430 if ((scl_i_q && (!scl_i))) -8-: 431 if (((scl_i_q && scl_i) && (sda_i_q != sda_i))) -9-: 454 if (((((!scl_i_q) && scl_i) && sda_i) && (!fmt_flag_nak_ok_i))) -10-: 456 if ((scl_i_q && (!scl_i))) -11-: 457 if (((scl_i_q && scl_i) && (sda_i_q != sda_i))) -12-: 479 if ((scl_i_q && (!scl_i))) -13-: 480 if (((scl_i_q && scl_i) && (sda_i_q != sda_i))) -14-: 489 if (((bit_index == '0) && (tcount_q == 16'b1))) -15-: 502 if (fmt_flag_read_continue_i) -16-: 503 if ((byte_index == 9'b1)) -17-: 509 if (fmt_flag_read_continue_i) -18-: 510 if ((byte_index == 9'b1)) -19-: 515 if ((scl_i_q && (!scl_i))) -20-: 516 if (((scl_i_q && scl_i) && (sda_i_q != sda_i))) -21-: 524 if (fmt_flag_read_continue_i) -22-: 525 if ((byte_index == 9'b1)) -23-: 544 if (((!scl_i) && scl_i_q)) -24-: 555 if (((!sda_i) && (!scl_i))) -25-: 558 if (sda_i) -26-: 575 if (fmt_flag_stop_after_i)

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13--14--15--16--17--18--19--20--21--22--23--24--25--26-StatusTests
Idle 1 - - - - - - - - - - - - - - - - - - - - - - - - Covered T26,T27,T28
Idle 0 - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
SetupStart - 1 - - - - - - - - - - - - - - - - - - - - - - - Not Covered
SetupStart - 0 1 - - - - - - - - - - - - - - - - - - - - - - Covered T4,T14,T15
SetupStart - 0 0 - - - - - - - - - - - - - - - - - - - - - - Covered T4,T14,T15
HoldStart - - - 1 - - - - - - - - - - - - - - - - - - - - - Not Covered
HoldStart - - - 0 - - - - - - - - - - - - - - - - - - - - - Covered T4,T14,T15
ClockStart - - - - - - - - - - - - - - - - - - - - - - - - - Covered T4,T14,T15
ClockLow - - - - 1 - - - - - - - - - - - - - - - - - - - - Covered T15,T25,T17
ClockLow - - - - 0 - - - - - - - - - - - - - - - - - - - - Covered T4,T14,T15
ClockPulse - - - - - 1 - - - - - - - - - - - - - - - - - - - Not Covered
ClockPulse - - - - - 0 - - - - - - - - - - - - - - - - - - - Covered T4,T14,T15
ClockPulse - - - - - - 1 - - - - - - - - - - - - - - - - - - Covered T23,T24,T20
ClockPulse - - - - - - 0 - - - - - - - - - - - - - - - - - - Covered T4,T14,T15
HoldBit - - - - - - - - - - - - - - - - - - - - - - - - - Covered T4,T14,T15
ClockLowAck - - - - - - - - - - - - - - - - - - - - - - - - - Covered T4,T14,T15
ClockPulseAck - - - - - - - 1 - - - - - - - - - - - - - - - - - Covered T26,T27,T28
ClockPulseAck - - - - - - - 0 - - - - - - - - - - - - - - - - - Covered T4,T14,T15
ClockPulseAck - - - - - - - - 1 - - - - - - - - - - - - - - - - Covered T23,T24,T20
ClockPulseAck - - - - - - - - 0 - - - - - - - - - - - - - - - - Covered T4,T14,T15
ClockPulseAck - - - - - - - - - 1 - - - - - - - - - - - - - - - Covered T23,T24,T20
ClockPulseAck - - - - - - - - - 0 - - - - - - - - - - - - - - - Covered T4,T14,T15
HoldDevAck - - - - - - - - - - - - - - - - - - - - - - - - - Covered T4,T14,T15
ReadClockLow - - - - - - - - - - - - - - - - - - - - - - - - - Covered T4,T14,T16
ReadClockPulse - - - - - - - - - - 1 - - - - - - - - - - - - - - Not Covered
ReadClockPulse - - - - - - - - - - 0 - - - - - - - - - - - - - - Covered T4,T14,T16
ReadClockPulse - - - - - - - - - - - 1 - - - - - - - - - - - - - Covered T33,T34
ReadClockPulse - - - - - - - - - - - 0 - - - - - - - - - - - - - Covered T4,T14,T16
ReadHoldBit - - - - - - - - - - - - 1 - - - - - - - - - - - - Covered T4,T14,T16
ReadHoldBit - - - - - - - - - - - - 0 - - - - - - - - - - - - Covered T4,T14,T16
HostClockLowAck - - - - - - - - - - - - - 1 - - - - - - - - - - - Covered T17,T44,T23
HostClockLowAck - - - - - - - - - - - - - 0 1 - - - - - - - - - - Covered T4,T14,T16
HostClockLowAck - - - - - - - - - - - - - 0 0 - - - - - - - - - - Covered T4,T14,T16
HostClockPulseAck - - - - - - - - - - - - - - - 1 - - - - - - - - - Covered T17,T44,T23
HostClockPulseAck - - - - - - - - - - - - - - - 0 1 - - - - - - - - Covered T4,T14,T16
HostClockPulseAck - - - - - - - - - - - - - - - 0 0 - - - - - - - - Covered T4,T14,T16
HostClockPulseAck - - - - - - - - - - - - - - - - - 1 - - - - - - - Not Covered
HostClockPulseAck - - - - - - - - - - - - - - - - - 0 - - - - - - - Covered T4,T14,T16
HostClockPulseAck - - - - - - - - - - - - - - - - - - 1 - - - - - - Not Covered
HostClockPulseAck - - - - - - - - - - - - - - - - - - 0 - - - - - - Covered T4,T14,T16
HostHoldBitAck - - - - - - - - - - - - - - - - - - - 1 - - - - - Covered T17,T44,T23
HostHoldBitAck - - - - - - - - - - - - - - - - - - - 0 1 - - - - Covered T4,T14,T16
HostHoldBitAck - - - - - - - - - - - - - - - - - - - 0 0 - - - - Covered T4,T14,T16
ClockStop - - - - - - - - - - - - - - - - - - - - - - - - - Covered T4,T14,T15
SetupStop - - - - - - - - - - - - - - - - - - - - - 1 - - - Not Covered
SetupStop - - - - - - - - - - - - - - - - - - - - - 0 - - - Covered T4,T14,T15
HoldStop - - - - - - - - - - - - - - - - - - - - - - 1 - - Not Covered
HoldStop - - - - - - - - - - - - - - - - - - - - - - 0 1 - Covered T4,T14,T15
HoldStop - - - - - - - - - - - - - - - - - - - - - - 0 0 - Covered T4,T14,T15
Active - - - - - - - - - - - - - - - - - - - - - - - - - Covered T4,T14,T15
PopFmtFifo - - - - - - - - - - - - - - - - - - - - - - - - 1 Covered T4,T14,T15
PopFmtFifo - - - - - - - - - - - - - - - - - - - - - - - - 0 Covered T4,T14,T15
default - - - - - - - - - - - - - - - - - - - - - - - - - Not Covered


LineNo. Expression -1-: 614 case (state_q) -2-: 618 if (host_enable_i) -3-: 619 if (((unhandled_unexp_nak_i || unhandled_nak_timeout_i) || halt_controller_i)) -4-: 632 if ((trans_started && unhandled_nak_cnt_expired)) -5-: 639 if (fmt_fifo_rvalid_i) -6-: 640 if ((trans_started || bus_free_i)) -7-: 644 if ((trans_started && (!host_enable_i))) -8-: 658 if (((!trans_started) && (!scl_i))) -9-: 662 if ((((trans_started && (!scl_i)) && (!scl_i_q)) && stretch_predict_cnt_expired)) -10-: 668 if (((trans_started && (!scl_i)) && scl_i_q)) -11-: 671 if ((tcount_q == 16'b1)) -12-: 679 if (((tcount_q == 16'b1) || ((!scl_i) && scl_i_q))) -13-: 687 if ((tcount_q == 16'b1)) -14-: 695 if ((tcount_q == 16'b1)) -15-: 697 if (pend_restart) -16-: 708 if ((((!scl_i) && (!scl_i_q)) && stretch_predict_cnt_expired)) -17-: 712 if (((scl_i_q && scl_i) && (sda_i_q != sda_i))) -18-: 715 if (((tcount_q == 16'b1) || ((!scl_i) && scl_i_q))) -19-: 725 if ((tcount_q == 16'b1)) -20-: 728 if ((bit_index == '0)) -21-: 740 if ((tcount_q == 16'b1)) -22-: 748 if ((((!scl_i) && (!scl_i_q)) && stretch_predict_cnt_expired)) -23-: 752 if (((scl_i_q && scl_i) && (sda_i_q != sda_i))) -24-: 756 if (((tcount_q == 16'b1) || ((!scl_i) && scl_i_q))) -25-: 765 if ((tcount_q == 16'b1)) -26-: 766 if (fmt_flag_stop_after_i) -27-: 779 if ((tcount_q == 16'b1)) -28-: 787 if ((((!scl_i) && (!scl_i_q)) && stretch_predict_cnt_expired)) -29-: 791 if (((scl_i_q && scl_i) && (sda_i_q != sda_i))) -30-: 794 if (((tcount_q == 16'b1) || ((!scl_i) && scl_i_q))) -31-: 803 if ((tcount_q == 16'b1)) -32-: 806 if ((bit_index == '0)) -33-: 819 if ((tcount_q == 16'b1)) -34-: 827 if ((((!scl_i) && (!scl_i_q)) && stretch_predict_cnt_expired)) -35-: 831 if (((scl_i_q && scl_i) && (sda_i_q != sda_i))) -36-: 834 if (((tcount_q == 16'b1) || ((!scl_i) && scl_i_q))) -37-: 842 if ((tcount_q == 16'b1)) -38-: 843 if ((byte_index == 9'b1)) -39-: 844 if (fmt_flag_stop_after_i) -40-: 863 if ((tcount_q == 16'b1)) -41-: 871 if ((((!scl_i) && (!scl_i_q)) && stretch_predict_cnt_expired)) -42-: 875 if (((!scl_i) && scl_i_q)) -43-: 878 if ((tcount_q == 16'b1)) -44-: 884 if (((!sda_i) && (!scl_i))) -45-: 888 if (sda_i) -46-: 890 if (auto_stop_q) -47-: 904 if (fmt_flag_read_bytes_i) -48-: 909 if ((fmt_flag_start_before_i && (!trans_started))) -49-: 922 if (((!host_enable_i) && trans_started)) -50-: 927 if (((((!host_enable_i) || (fmt_fifo_depth_i == 7'b1)) || unhandled_unexp_nak_i) || (!trans_started)))

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13--14--15--16--17--18--19--20--21--22--23--24--25--26--27--28--29--30--31--32--33--34--35--36--37--38--39--40--41--42--43--44--45--46--47--48--49--50-StatusTests
Idle 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Not Covered
Idle 1 1 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T23,T24,T26
Idle 1 0 - 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T4,T14,T15
Idle 1 0 - 1 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T39,T40,T41
Idle 1 0 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T4,T14,T15
Idle 0 - - - - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Not Covered
Idle 0 - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
SetupStart - - - - - - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Not Covered
SetupStart - - - - - - 0 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Not Covered
SetupStart - - - - - - 0 0 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Not Covered
SetupStart - - - - - - 0 0 0 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T4,T14,T15
SetupStart - - - - - - 0 0 0 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T4,T14,T15
HoldStart - - - - - - - - - - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T4,T14,T15
HoldStart - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T4,T14,T15
ClockStart - - - - - - - - - - - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T4,T14,T15
ClockStart - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T4,T15,T16
ClockLow - - - - - - - - - - - - 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T15,T25,T17
ClockLow - - - - - - - - - - - - 1 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T4,T14,T15
ClockLow - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T4,T14,T15
ClockPulse - - - - - - - - - - - - - - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Not Covered
ClockPulse - - - - - - - - - - - - - - 0 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T23,T24,T20
ClockPulse - - - - - - - - - - - - - - 0 0 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T4,T14,T15
ClockPulse - - - - - - - - - - - - - - 0 0 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T4,T14,T15
HoldBit - - - - - - - - - - - - - - - - - 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T4,T14,T15
HoldBit - - - - - - - - - - - - - - - - - 1 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T4,T14,T15
HoldBit - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T4,T14,T15
ClockLowAck - - - - - - - - - - - - - - - - - - - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T4,T14,T15
ClockLowAck - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T4,T14,T15
ClockPulseAck - - - - - - - - - - - - - - - - - - - - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T4,T14,T15
ClockPulseAck - - - - - - - - - - - - - - - - - - - - 0 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T23,T24,T20
ClockPulseAck - - - - - - - - - - - - - - - - - - - - 0 0 1 - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T4,T14,T15
ClockPulseAck - - - - - - - - - - - - - - - - - - - - 0 0 0 - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T4,T14,T15
HoldDevAck - - - - - - - - - - - - - - - - - - - - - - - 1 1 - - - - - - - - - - - - - - - - - - - - - - - - Covered T4,T15,T35
HoldDevAck - - - - - - - - - - - - - - - - - - - - - - - 1 0 - - - - - - - - - - - - - - - - - - - - - - - - Covered T4,T14,T15
HoldDevAck - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - Covered T4,T14,T15
ReadClockLow - - - - - - - - - - - - - - - - - - - - - - - - - 1 - - - - - - - - - - - - - - - - - - - - - - - Covered T4,T14,T16
ReadClockLow - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - Covered T4,T14,T16
ReadClockPulse - - - - - - - - - - - - - - - - - - - - - - - - - - 1 - - - - - - - - - - - - - - - - - - - - - - Not Covered
ReadClockPulse - - - - - - - - - - - - - - - - - - - - - - - - - - 0 1 - - - - - - - - - - - - - - - - - - - - - Covered T33,T34
ReadClockPulse - - - - - - - - - - - - - - - - - - - - - - - - - - 0 0 1 - - - - - - - - - - - - - - - - - - - - Covered T4,T14,T16
ReadClockPulse - - - - - - - - - - - - - - - - - - - - - - - - - - 0 0 0 - - - - - - - - - - - - - - - - - - - - Covered T4,T14,T16
ReadHoldBit - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 - - - - - - - - - - - - - - - - - - Covered T4,T14,T16
ReadHoldBit - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 0 - - - - - - - - - - - - - - - - - - Covered T4,T14,T16
ReadHoldBit - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - Covered T4,T14,T16
HostClockLowAck - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 - - - - - - - - - - - - - - - - - Covered T4,T14,T16
HostClockLowAck - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - Covered T4,T14,T16
HostClockPulseAck - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 - - - - - - - - - - - - - - - - Not Covered
HostClockPulseAck - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 1 - - - - - - - - - - - - - - - Not Covered
HostClockPulseAck - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 0 1 - - - - - - - - - - - - - - Covered T4,T14,T16
HostClockPulseAck - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 0 0 - - - - - - - - - - - - - - Covered T4,T14,T16
HostHoldBitAck - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 - - - - - - - - - - - Covered T4,T14,T16
HostHoldBitAck - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 0 - - - - - - - - - - - Covered T17,T44,T23
HostHoldBitAck - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 0 - - - - - - - - - - - - Covered T4,T14,T16
HostHoldBitAck - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - Covered T4,T14,T16
ClockStop - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 - - - - - - - - - - Covered T4,T14,T15
ClockStop - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - Covered T4,T14,T15
SetupStop - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 - - - - - - - - - Not Covered
SetupStop - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 1 - - - - - - - - Not Covered
SetupStop - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 0 1 - - - - - - - Covered T4,T14,T15
SetupStop - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 0 0 - - - - - - - Covered T4,T14,T15
HoldStop - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 - - - - - - Not Covered
HoldStop - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 1 1 - - - - Not Covered
HoldStop - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 1 0 - - - - Covered T4,T14,T15
HoldStop - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 0 - - - - - Covered T4,T14,T15
Active - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 - - - Covered T4,T14,T16
Active - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 1 - - Covered T4,T14,T15
Active - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 0 - - Covered T4,T15,T35
PopFmtFifo - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 - Not Covered
PopFmtFifo - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 1 Covered T4,T14,T15
PopFmtFifo - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 0 Covered T4,T14,T15
default - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Not Covered


LineNo. Expression -1-: 954 if ((trans_started && (sda_interference_i || ctrl_symbol_failed)))

Branches:
-1-StatusTests
1 Covered T20,T21,T22
0 Covered T1,T2,T3


LineNo. Expression -1-: 961 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : i2c_controller_fsm
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SclOutputGlitch_A 412269125 3845160 0 0


SclOutputGlitch_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412269125 3845160 0 0
T4 123450 5098 0 0
T5 396485 0 0 0
T6 39172 0 0 0
T7 143641 0 0 0
T8 75281 0 0 0
T9 77169 0 0 0
T10 88189 0 0 0
T14 5349 91 0 0
T15 199360 8687 0 0
T16 233733 11305 0 0
T17 0 42532 0 0
T25 0 10480 0 0
T35 0 3315 0 0
T43 0 23440 0 0
T45 0 37 0 0
T46 0 586 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%