Group : tb.dut.u_i2c_protocol_cov::i2c_cmd_complete_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tb.dut.u_i2c_protocol_cov::i2c_cmd_complete_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_sva_0.1/i2c_protocol_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
i2c_protocol_cov.unnamed$$_0.cmd_complete_cg 100.00 1 100 1 64 64




Group Instance : i2c_protocol_cov.unnamed$$_0.cmd_complete_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance i2c_protocol_cov.unnamed$$_0.cmd_complete_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 3 0 3 100.00
Crosses 4 0 4 100.00


Variables for Group Instance i2c_protocol_cov.unnamed$$_0.cmd_complete_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_cmd_complete 1 0 1 100.00 100 1 1 0
cp_ip_mode 2 0 2 100.00 100 1 1 0


Crosses for Group Instance i2c_protocol_cov.unnamed$$_0.cmd_complete_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_read_x_complete 2 0 2 100.00 100 1 1 0
cp_write_x_complete 2 0 2 100.00 100 1 1 0


Summary for Variable cp_cmd_complete

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_cmd_complete

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
complete 1561 1 T1 1 T2 1 T3 1



Summary for Variable cp_ip_mode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_ip_mode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
device 1006 1 T2 1 T3 1 T4 1
host 555 1 T1 1 T8 1 T9 1



Summary for Cross cp_read_x_complete

Samples crossed: cp_cmd_complete cp_ip_mode
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 2 0 2 100.00


Automatically Generated Cross Bins for cp_read_x_complete

Bins
cp_cmd_completecp_ip_modeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
complete device 414 1 T5 1 T42 1 T48 1
complete host 233 1 T1 1 T22 1 T23 1



Summary for Cross cp_write_x_complete

Samples crossed: cp_cmd_complete cp_ip_mode
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 2 0 2 100.00


Automatically Generated Cross Bins for cp_write_x_complete

Bins
cp_cmd_completecp_ip_modeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
complete device 550 1 T2 1 T3 1 T4 1
complete host 321 1 T8 1 T9 1 T14 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%