Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	35681523	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

8834405

1

T1

10055

T2

15

T3

38

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	43592512	1			T1	20891		T2	3		T3	4
values[0x0]	461841	1			T1	86		T2	10		T3	46
values[0x1]	461575	1			T1	86		T2	7		T3	34

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	24885406	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

19630522

1

T1

12362

T2

16

T3

48

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	168966	1			T1	69		T8	99		T9	6
valid_sources[0x01]	165077	1			T1	73		T8	129		T9	4
valid_sources[0x02]	175029	1			T1	65		T6	3		T8	81
valid_sources[0x03]	167820	1			T1	96		T6	3		T8	95
valid_sources[0x04]	177859	1			T1	81		T8	104		T9	5
valid_sources[0x05]	179319	1			T1	80		T8	88		T9	8
valid_sources[0x06]	172583	1			T1	89		T8	89		T9	7
valid_sources[0x07]	163461	1			T1	65		T8	94		T9	11
valid_sources[0x08]	179779	1			T1	96		T8	93		T9	4
valid_sources[0x09]	163081	1			T1	91		T8	112		T9	13
valid_sources[0x0a]	170954	1			T1	87		T8	100		T9	6
valid_sources[0x0b]	158516	1			T1	101		T8	94		T9	20
valid_sources[0x0c]	176934	1			T1	86		T8	111		T9	5
valid_sources[0x0d]	175417	1			T1	79		T7	8		T8	92
valid_sources[0x0e]	161892	1			T1	83		T8	99		T9	13
valid_sources[0x0f]	164966	1			T1	70		T8	89		T48	86
valid_sources[0x10]	168467	1			T1	77		T8	100		T9	6
valid_sources[0x11]	179010	1			T1	76		T8	90		T9	14
valid_sources[0x12]	179371	1			T1	91		T8	116		T9	12
valid_sources[0x13]	180639	1			T1	65		T8	105		T9	6
valid_sources[0x14]	193490	1			T1	75		T8	112		T9	16
valid_sources[0x15]	185442	1			T1	91		T8	84		T9	8
valid_sources[0x16]	192898	1			T1	86		T8	91		T9	7
valid_sources[0x17]	169789	1			T1	87		T8	86		T9	9
valid_sources[0x18]	156475	1			T1	92		T8	92		T9	4
valid_sources[0x19]	174190	1			T1	68		T8	90		T9	8
valid_sources[0x1a]	184260	1			T1	84		T2	2		T8	91
valid_sources[0x1b]	168403	1			T1	91		T8	102		T9	3
valid_sources[0x1c]	193710	1			T1	105		T8	103		T9	7
valid_sources[0x1d]	168441	1			T1	80		T8	80		T9	9
valid_sources[0x1e]	173321	1			T1	106		T8	98		T9	6
valid_sources[0x1f]	168263	1			T1	74		T8	95		T9	10
valid_sources[0x20]	159332	1			T1	81		T8	79		T9	8
valid_sources[0x21]	179148	1			T1	73		T8	77		T9	10
valid_sources[0x22]	165979	1			T1	102		T8	100		T9	10
valid_sources[0x23]	177933	1			T1	77		T8	89		T9	9
valid_sources[0x24]	307504	1			T1	62		T8	84		T9	8
valid_sources[0x25]	196797	1			T1	77		T8	83		T9	11
valid_sources[0x26]	183552	1			T1	82		T6	2		T8	75
valid_sources[0x27]	162683	1			T1	70		T8	87		T9	14
valid_sources[0x28]	177431	1			T1	96		T7	4		T8	88
valid_sources[0x29]	171100	1			T1	78		T8	107		T9	6
valid_sources[0x2a]	174759	1			T1	80		T8	85		T9	11
valid_sources[0x2b]	170528	1			T1	65		T8	89		T9	4
valid_sources[0x2c]	181895	1			T1	103		T2	2		T8	93
valid_sources[0x2d]	185746	1			T1	89		T8	93		T9	22
valid_sources[0x2e]	163366	1			T1	88		T8	82		T9	10
valid_sources[0x2f]	195608	1			T1	59		T8	94		T9	4
valid_sources[0x30]	188749	1			T1	67		T8	102		T9	11
valid_sources[0x31]	157837	1			T1	82		T8	97		T9	8
valid_sources[0x32]	160267	1			T1	93		T8	85		T9	3
valid_sources[0x33]	151736	1			T1	92		T8	102		T9	9
valid_sources[0x34]	178047	1			T1	82		T8	83		T9	6
valid_sources[0x35]	165359	1			T1	92		T7	4		T8	95
valid_sources[0x36]	171812	1			T1	62		T8	97		T9	6
valid_sources[0x37]	166843	1			T1	77		T8	95		T9	3
valid_sources[0x38]	175396	1			T1	97		T8	91		T9	12
valid_sources[0x39]	174880	1			T1	87		T8	94		T9	1
valid_sources[0x3a]	151481	1			T1	74		T8	81		T9	9
valid_sources[0x3b]	163871	1			T1	67		T8	104		T9	2
valid_sources[0x3c]	189320	1			T1	107		T8	103		T9	11
valid_sources[0x3d]	171472	1			T1	91		T8	100		T9	9
valid_sources[0x3e]	177413	1			T1	78		T8	100		T9	6
valid_sources[0x3f]	167258	1			T1	98		T6	1		T8	111
valid_sources[0x40]	193057	1			T1	89		T8	90		T9	7
valid_sources[0x41]	167205	1			T1	82		T8	111		T9	8
valid_sources[0x42]	181940	1			T1	107		T8	84		T9	8
valid_sources[0x43]	182089	1			T1	81		T8	106		T9	11
valid_sources[0x44]	173423	1			T1	94		T8	81		T9	15
valid_sources[0x45]	177552	1			T1	75		T8	92		T9	5
valid_sources[0x46]	166201	1			T1	60		T8	86		T9	9
valid_sources[0x47]	172858	1			T1	70		T8	89		T9	11
valid_sources[0x48]	168344	1			T1	95		T8	95		T9	10
valid_sources[0x49]	185673	1			T1	77		T8	97		T9	10
valid_sources[0x4a]	192916	1			T1	104		T8	106		T9	10
valid_sources[0x4b]	174932	1			T1	81		T8	76		T9	6
valid_sources[0x4c]	166769	1			T1	81		T8	90		T9	4
valid_sources[0x4d]	166189	1			T1	84		T8	82		T9	6
valid_sources[0x4e]	190287	1			T1	96		T8	84		T9	6
valid_sources[0x4f]	171419	1			T1	71		T8	76		T9	7
valid_sources[0x50]	168132	1			T1	101		T8	76		T9	8
valid_sources[0x51]	173139	1			T1	89		T8	111		T9	5
valid_sources[0x52]	176736	1			T1	69		T8	110		T9	12
valid_sources[0x53]	186378	1			T1	103		T8	91		T9	11
valid_sources[0x54]	178782	1			T1	91		T3	82		T7	1
valid_sources[0x55]	188340	1			T1	74		T8	89		T9	10
valid_sources[0x56]	181846	1			T1	80		T8	87		T9	4
valid_sources[0x57]	155311	1			T1	68		T8	87		T9	13
valid_sources[0x58]	169504	1			T1	101		T8	93		T9	5
valid_sources[0x59]	175364	1			T1	111		T8	96		T9	8
valid_sources[0x5a]	170011	1			T1	94		T8	94		T9	12
valid_sources[0x5b]	170781	1			T1	73		T8	83		T9	12
valid_sources[0x5c]	197401	1			T1	92		T8	91		T9	9
valid_sources[0x5d]	175111	1			T1	90		T8	67		T9	12
valid_sources[0x5e]	171248	1			T1	94		T8	93		T9	18
valid_sources[0x5f]	165159	1			T1	100		T4	3		T8	103
valid_sources[0x60]	172904	1			T1	94		T8	97		T9	5
valid_sources[0x61]	174247	1			T1	86		T8	92		T9	7
valid_sources[0x62]	186593	1			T1	97		T8	113		T9	16
valid_sources[0x63]	168829	1			T1	87		T8	79		T9	7
valid_sources[0x64]	170900	1			T1	83		T2	1		T8	75
valid_sources[0x65]	188290	1			T1	85		T8	81		T9	14
valid_sources[0x66]	172598	1			T1	66		T8	85		T9	11
valid_sources[0x67]	184162	1			T1	84		T8	95		T9	14
valid_sources[0x68]	169255	1			T1	73		T8	91		T9	11
valid_sources[0x69]	181043	1			T1	74		T8	91		T9	8
valid_sources[0x6a]	167992	1			T1	70		T8	85		T9	9
valid_sources[0x6b]	170815	1			T1	101		T8	79		T9	8
valid_sources[0x6c]	175408	1			T1	76		T8	81		T9	4
valid_sources[0x6d]	202839	1			T1	84		T8	107		T9	9
valid_sources[0x6e]	171578	1			T1	96		T8	78		T9	16
valid_sources[0x6f]	174743	1			T1	88		T8	114		T9	8
valid_sources[0x70]	187457	1			T1	83		T8	81		T9	3
valid_sources[0x71]	167911	1			T1	89		T8	85		T9	5
valid_sources[0x72]	191819	1			T1	90		T8	93		T9	8
valid_sources[0x73]	174746	1			T1	95		T8	102		T9	11
valid_sources[0x74]	162598	1			T1	76		T8	74		T9	3
valid_sources[0x75]	183372	1			T1	66		T8	71		T9	7
valid_sources[0x76]	162388	1			T1	86		T8	85		T9	4
valid_sources[0x77]	161912	1			T1	79		T8	75		T9	6
valid_sources[0x78]	178480	1			T1	67		T8	95		T9	10
valid_sources[0x79]	158529	1			T1	88		T8	92		T9	17
valid_sources[0x7a]	172977	1			T1	77		T8	99		T9	9
valid_sources[0x7b]	181882	1			T1	88		T8	84		T9	4
valid_sources[0x7c]	175004	1			T1	77		T8	92		T9	5
valid_sources[0x7d]	173068	1			T1	63		T8	95		T9	8
valid_sources[0x7e]	161164	1			T1	72		T8	74		T9	4
valid_sources[0x7f]	169509	1			T1	85		T8	89		T9	11
valid_sources[0x80]	171832	1			T1	92		T8	80		T9	10

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

8433994

1

T1

9922

T2

2

T3

1

values[0x0]

all_enables

biggest_size

239749

1

T1

69

T2

8

T3

25

values[0x1]

all_enables

biggest_size

160662

1

T1

64

T2

5

T3

12