Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.48	100.00	100.00	93.91			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	447117244	0	0	0
ctrl_rd_A	447117244	3509	0	0
host_fifo_config_rd_A	447117244	6321	0	0
host_nack_handler_timeout_rd_A	447117244	1970	0	0
host_timeout_ctrl_rd_A	447117244	1773	0	0
intr_enable_rd_A	447117244	6223	0	0
ovrd_rd_A	447117244	3207	0	0
target_fifo_config_rd_A	447117244	2050	0	0
target_id_rd_A	447117244	2635	0	0
target_timeout_ctrl_rd_A	447117244	2070	0	0
timeout_ctrl_rd_A	447117244	2556	0	0
timing0_rd_A	447117244	2087	0	0
timing1_rd_A	447117244	2013	0	0
timing2_rd_A	447117244	2008	0	0
timing3_rd_A	447117244	1952	0	0
timing4_rd_A	447117244	2021	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447117244	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447117244	3509	0	0
T103	14903	160	0	0
T104	2415	13	0	0
T105	3857	29	0	0
T106	2738	52	0	0
T107	3527	20	0	0
T108	12901	34	0	0
T109	13586	371	0	0
T110	2947	56	0	0
T111	6142	23	0	0
T112	13462	220	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447117244	6321	0	0
T24	152400	310	0	0
T33	406210	0	0	0
T45	14638	0	0	0
T51	44522	0	0	0
T58	310309	0	0	0
T59	389486	0	0	0
T113	0	125	0	0
T114	0	150	0	0
T115	0	256	0	0
T116	0	143	0	0
T117	0	140	0	0
T118	0	213	0	0
T119	0	163	0	0
T120	0	171	0	0
T121	0	167	0	0
T122	1024	0	0	0
T123	71361	0	0	0
T124	84062	0	0	0
T125	27088	0	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447117244	1970	0	0
T103	14903	46	0	0
T104	2415	8	0	0
T105	3857	12	0	0
T106	2738	3	0	0
T107	3527	27	0	0
T108	12901	65	0	0
T109	13586	128	0	0
T110	2947	15	0	0
T111	6142	30	0	0
T112	13462	75	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447117244	1773	0	0
T103	14903	36	0	0
T104	2415	7	0	0
T105	3857	52	0	0
T106	2738	8	0	0
T107	3527	37	0	0
T108	12901	34	0	0
T109	13586	99	0	0
T110	2947	5	0	0
T111	6142	15	0	0
T112	13462	69	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447117244	6223	0	0
T24	152400	29	0	0
T33	406210	0	0	0
T45	14638	0	0	0
T51	44522	0	0	0
T58	310309	0	0	0
T59	389486	0	0	0
T103	0	285	0	0
T122	1024	0	0	0
T123	71361	0	0	0
T124	84062	0	0	0
T125	27088	0	0	0
T126	0	30	0	0
T127	0	13	0	0
T128	0	12	0	0
T129	0	23	0	0
T130	0	20	0	0
T131	0	16	0	0
T132	0	5	0	0
T133	0	13	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447117244	3207	0	0
T35	10557	0	0	0
T68	107117	0	0	0
T96	1923	49	0	0
T100	14491	0	0	0
T101	195952	0	0	0
T134	0	59	0	0
T135	0	31	0	0
T136	0	25	0	0
T137	0	20	0	0
T138	0	19	0	0
T139	0	52	0	0
T140	0	19	0	0
T141	0	76	0	0
T142	0	44	0	0
T143	35498	0	0	0
T144	735	0	0	0
T145	48582	0	0	0
T146	10092	0	0	0
T147	45453	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447117244	2050	0	0
T103	14903	44	0	0
T104	2415	1	0	0
T105	3857	5	0	0
T106	2738	8	0	0
T107	3527	38	0	0
T108	12901	29	0	0
T109	13586	120	0	0
T110	2947	18	0	0
T111	6142	42	0	0
T112	13462	114	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447117244	2635	0	0
T103	14903	103	0	0
T105	3857	41	0	0
T106	2738	9	0	0
T107	3527	1	0	0
T108	12901	28	0	0
T109	13586	169	0	0
T110	2947	18	0	0
T111	6142	11	0	0
T112	13462	183	0	0
T148	4553	8	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447117244	2070	0	0
T103	14903	28	0	0
T104	2415	5	0	0
T106	2738	8	0	0
T107	3527	4	0	0
T108	12901	12	0	0
T109	13586	135	0	0
T110	2947	4	0	0
T111	6142	56	0	0
T112	13462	144	0	0
T148	4553	2	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447117244	2556	0	0
T103	14903	126	0	0
T105	3857	14	0	0
T106	2738	7	0	0
T107	3527	29	0	0
T108	12901	73	0	0
T109	13586	153	0	0
T110	2947	8	0	0
T111	6142	32	0	0
T112	13462	128	0	0
T148	4553	10	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447117244	2087	0	0
T103	14903	76	0	0
T104	2415	14	0	0
T105	3857	13	0	0
T106	2738	8	0	0
T107	3527	10	0	0
T108	12901	40	0	0
T109	13586	95	0	0
T110	2947	14	0	0
T111	6142	29	0	0
T112	13462	124	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447117244	2013	0	0
T103	14903	92	0	0
T104	2415	3	0	0
T105	3857	9	0	0
T106	2738	6	0	0
T107	3527	4	0	0
T108	12901	20	0	0
T109	13586	100	0	0
T110	2947	8	0	0
T111	6142	77	0	0
T112	13462	115	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447117244	2008	0	0
T103	14903	66	0	0
T105	3857	12	0	0
T106	2738	8	0	0
T107	3527	15	0	0
T108	12901	32	0	0
T109	13586	116	0	0
T110	2947	28	0	0
T111	6142	32	0	0
T112	13462	93	0	0
T148	4553	2	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447117244	1952	0	0
T103	14903	52	0	0
T104	2415	5	0	0
T105	3857	39	0	0
T106	2738	8	0	0
T107	3527	21	0	0
T108	12901	39	0	0
T109	13586	105	0	0
T110	2947	9	0	0
T111	6142	45	0	0
T112	13462	112	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447117244	2021	0	0
T103	14903	66	0	0
T104	2415	9	0	0
T105	3857	3	0	0
T106	2738	20	0	0
T108	12901	32	0	0
T109	13586	120	0	0
T110	2947	24	0	0
T111	6142	79	0	0
T112	13462	137	0	0
T149	3511	27	0	0