Unified Coverage Report :: Group :: i2c_env_pkg::i2c_status_cg

Group : i2c_env_pkg::i2c_status_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.status_cg	100.00	1	100	1	64	64

---

Group Instance : i2c_env_pkg.status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00

Variables for Group Instance i2c_env_pkg.status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_acqempty	2	0	2	100.00	100	1	1	2
cp_acqfull	2	0	2	100.00	100	1	1	2
cp_fmtempty	2	0	2	100.00	100	1	1	2
cp_fmtfull	2	0	2	100.00	100	1	1	2
cp_hostidle	2	0	2	100.00	100	1	1	2
cp_rxempty	2	0	2	100.00	100	1	1	2
cp_rxfull	2	0	2	100.00	100	1	1	2
cp_targetidle	2	0	2	100.00	100	1	1	2
cp_txempty	2	0	2	100.00	100	1	1	2
cp_txfull	2	0	2	100.00	100	1	1	2

Summary for Variable cp_acqempty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_acqempty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1314048

1

T4

3594

T5

514

T9

10

auto[1]

28959404

1

T1

584

T2

2609

T3

1372

---

Summary for Variable cp_acqfull

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_acqfull

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30250081

1

T1

584

T2

2609

T3

1372

auto[1]

23371

1

T52

150

T54

368

T55

329

---

Summary for Variable cp_fmtempty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_fmtempty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28119345

1

T1

569

T2

2508

T3

1258

auto[1]

2154107

1

T1

15

T2

101

T3

114

---

Summary for Variable cp_fmtfull

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_fmtfull

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23834381

1

T1

584

T2

2609

T3

1372

auto[1]

6439071

1

T27

48278

T18

15348

T40

439

---

Summary for Variable cp_hostidle

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_hostidle

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28116064

1

T1

569

T2

2508

T3

1258

auto[1]

2157388

1

T1

15

T2

101

T3

114

---

Summary for Variable cp_rxempty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rxempty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6741539

1

T1

88

T2

275

T3

165

auto[1]

23531913

1

T1

496

T2

2334

T3

1207

---

Summary for Variable cp_rxfull

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rxfull

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30211311

1

T1

584

T2

2609

T3

1372

auto[1]

62141

1

T27

63

T18

459

T14

1705

---

Summary for Variable cp_targetidle

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_targetidle

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1859048

1

T4

3681

T5

540

T7

3

auto[1]

28414404

1

T1

584

T2

2609

T3

1372

---

Summary for Variable cp_txempty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_txempty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1733102

1

T4

3663

T5

375

T7

3

auto[1]

28540350

1

T1

584

T2

2609

T3

1372

---

Summary for Variable cp_txfull

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_txfull

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30273443

1

T1

584

T2

2609

T3

1372

auto[1]

9

1

T87

1

T71

2

T275

1