Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	26603867	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

7039005

1

T1

189

T2

840

T3

455

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	32916679	1			T1	638		T2	2779		T3	1447
values[0x0]	362504	1			T1	21		T2	100		T3	67
values[0x1]	363689	1			T1	30		T2	83		T3	94

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	18582031	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

15060841

1

T1

345

T2

1462

T3

757

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	123182	1			T2	13		T3	3		T4	10
valid_sources[0x01]	127977	1			T2	12		T3	11		T4	11
valid_sources[0x02]	130712	1			T2	11		T3	6		T4	24
valid_sources[0x03]	125892	1			T2	11		T3	7		T4	24
valid_sources[0x04]	131947	1			T2	8		T4	15		T6	26
valid_sources[0x05]	140639	1			T2	15		T3	7		T4	47
valid_sources[0x06]	125565	1			T1	21		T2	10		T3	20
valid_sources[0x07]	121468	1			T2	15		T3	10		T4	15
valid_sources[0x08]	134052	1			T2	4		T3	2		T4	21
valid_sources[0x09]	122677	1			T2	30		T4	9		T5	12
valid_sources[0x0a]	135961	1			T2	10		T3	10		T4	8
valid_sources[0x0b]	137300	1			T2	10		T4	7		T6	17
valid_sources[0x0c]	120847	1			T2	5		T3	21		T4	29
valid_sources[0x0d]	125220	1			T2	7		T3	19		T4	16
valid_sources[0x0e]	161412	1			T1	30		T2	9		T3	7
valid_sources[0x0f]	137224	1			T2	10		T3	4		T4	17
valid_sources[0x10]	129281	1			T2	5		T3	3		T4	9
valid_sources[0x11]	128236	1			T2	8		T3	2		T4	21
valid_sources[0x12]	144041	1			T2	9		T3	10		T4	18
valid_sources[0x13]	117895	1			T2	13		T3	2		T4	9
valid_sources[0x14]	136261	1			T1	19		T2	14		T3	3
valid_sources[0x15]	132076	1			T2	7		T3	4		T4	12
valid_sources[0x16]	123467	1			T2	23		T4	14		T5	8
valid_sources[0x17]	130848	1			T2	13		T3	2		T4	10
valid_sources[0x18]	146454	1			T1	50		T2	6		T3	1
valid_sources[0x19]	128302	1			T1	3		T2	8		T3	2
valid_sources[0x1a]	128084	1			T2	11		T3	4		T4	12
valid_sources[0x1b]	112964	1			T2	23		T4	22		T5	1
valid_sources[0x1c]	116493	1			T2	4		T3	5		T4	26
valid_sources[0x1d]	135642	1			T2	10		T3	5		T4	16
valid_sources[0x1e]	127408	1			T2	8		T4	27		T5	5
valid_sources[0x1f]	128075	1			T2	11		T3	17		T4	18
valid_sources[0x20]	118948	1			T1	1		T2	8		T3	4
valid_sources[0x21]	126411	1			T2	18		T3	16		T4	9
valid_sources[0x22]	143815	1			T2	8		T3	2		T4	8
valid_sources[0x23]	123501	1			T2	16		T3	10		T4	8
valid_sources[0x24]	132295	1			T1	1		T2	15		T3	3
valid_sources[0x25]	125471	1			T2	23		T3	4		T4	13
valid_sources[0x26]	166278	1			T2	11		T3	1		T4	26
valid_sources[0x27]	128025	1			T2	22		T3	1		T4	14
valid_sources[0x28]	126407	1			T2	7		T3	5		T4	10
valid_sources[0x29]	126536	1			T2	21		T3	14		T4	15
valid_sources[0x2a]	138084	1			T2	11		T3	3		T4	34
valid_sources[0x2b]	134923	1			T2	4		T3	3		T4	12
valid_sources[0x2c]	127712	1			T2	14		T3	5		T4	31
valid_sources[0x2d]	132078	1			T2	11		T3	2		T4	6
valid_sources[0x2e]	132194	1			T2	24		T3	20		T4	5
valid_sources[0x2f]	128663	1			T2	11		T3	10		T4	11
valid_sources[0x30]	122663	1			T2	3		T3	15		T4	12
valid_sources[0x31]	125311	1			T2	7		T3	2		T4	13
valid_sources[0x32]	127510	1			T1	1		T2	8		T3	3
valid_sources[0x33]	126547	1			T2	7		T3	2		T4	29
valid_sources[0x34]	126288	1			T2	15		T3	9		T4	11
valid_sources[0x35]	134469	1			T2	6		T3	10		T4	18
valid_sources[0x36]	131890	1			T2	10		T3	2		T4	13
valid_sources[0x37]	115546	1			T1	1		T2	4		T3	6
valid_sources[0x38]	127691	1			T2	19		T4	19		T5	3
valid_sources[0x39]	134238	1			T2	10		T3	17		T4	4
valid_sources[0x3a]	162389	1			T1	16		T2	6		T3	4
valid_sources[0x3b]	161168	1			T2	13		T3	5		T4	26
valid_sources[0x3c]	126958	1			T2	17		T3	3		T4	14
valid_sources[0x3d]	127351	1			T2	6		T3	2		T4	13
valid_sources[0x3e]	142288	1			T2	6		T4	9		T5	3
valid_sources[0x3f]	140042	1			T2	4		T3	10		T4	9
valid_sources[0x40]	134366	1			T2	18		T3	12		T4	20
valid_sources[0x41]	147084	1			T2	10		T3	1		T4	10
valid_sources[0x42]	127806	1			T2	12		T3	2		T4	22
valid_sources[0x43]	138785	1			T2	9		T3	12		T4	16
valid_sources[0x44]	142942	1			T2	15		T3	12		T4	19
valid_sources[0x45]	131180	1			T1	1		T2	20		T3	4
valid_sources[0x46]	121264	1			T2	9		T3	1		T4	15
valid_sources[0x47]	129346	1			T2	7		T3	12		T4	14
valid_sources[0x48]	137470	1			T2	16		T3	1		T4	8
valid_sources[0x49]	142464	1			T1	1		T2	23		T3	17
valid_sources[0x4a]	120441	1			T1	1		T2	10		T3	5
valid_sources[0x4b]	143494	1			T1	38		T2	9		T4	20
valid_sources[0x4c]	138430	1			T2	16		T4	17		T5	10
valid_sources[0x4d]	126684	1			T2	15		T3	7		T4	14
valid_sources[0x4e]	127715	1			T2	10		T3	9		T4	23
valid_sources[0x4f]	136353	1			T2	11		T3	5		T4	13
valid_sources[0x50]	143485	1			T2	6		T3	5		T4	12
valid_sources[0x51]	133121	1			T2	24		T3	9		T4	10
valid_sources[0x52]	129227	1			T2	8		T3	6		T4	20
valid_sources[0x53]	135212	1			T1	5		T2	5		T3	17
valid_sources[0x54]	142265	1			T1	1		T2	9		T3	8
valid_sources[0x55]	141940	1			T1	1		T2	8		T3	3
valid_sources[0x56]	134293	1			T2	14		T3	7		T4	12
valid_sources[0x57]	136869	1			T2	9		T3	2		T4	19
valid_sources[0x58]	122665	1			T2	16		T3	5		T4	6
valid_sources[0x59]	130148	1			T2	11		T3	1		T4	16
valid_sources[0x5a]	121734	1			T2	4		T4	13		T5	7
valid_sources[0x5b]	120320	1			T1	2		T2	9		T4	24
valid_sources[0x5c]	129086	1			T1	24		T2	15		T3	8
valid_sources[0x5d]	116550	1			T2	2		T3	11		T4	16
valid_sources[0x5e]	136062	1			T1	22		T2	20		T4	10
valid_sources[0x5f]	141561	1			T2	18		T3	6		T4	13
valid_sources[0x60]	121572	1			T2	13		T4	4		T5	9
valid_sources[0x61]	118818	1			T2	4		T3	11		T4	11
valid_sources[0x62]	123918	1			T2	14		T3	10		T4	13
valid_sources[0x63]	121605	1			T2	4		T3	10		T4	13
valid_sources[0x64]	123811	1			T2	4		T3	10		T4	5
valid_sources[0x65]	135665	1			T2	10		T3	2		T4	20
valid_sources[0x66]	132425	1			T2	10		T3	11		T4	11
valid_sources[0x67]	128741	1			T2	12		T3	1		T4	15
valid_sources[0x68]	147140	1			T2	17		T3	4		T4	11
valid_sources[0x69]	133983	1			T2	8		T3	7		T4	4
valid_sources[0x6a]	152043	1			T2	10		T3	4		T4	16
valid_sources[0x6b]	136777	1			T2	1		T3	9		T4	12
valid_sources[0x6c]	160864	1			T2	10		T3	16		T4	18
valid_sources[0x6d]	142343	1			T2	14		T3	8		T4	13
valid_sources[0x6e]	137412	1			T2	26		T3	3		T4	22
valid_sources[0x6f]	124404	1			T2	20		T3	8		T4	32
valid_sources[0x70]	126604	1			T2	21		T3	1		T4	15
valid_sources[0x71]	139866	1			T1	1		T2	17		T3	4
valid_sources[0x72]	125797	1			T2	6		T3	6		T4	13
valid_sources[0x73]	160770	1			T2	5		T3	5		T4	26
valid_sources[0x74]	140167	1			T1	1		T2	14		T3	9
valid_sources[0x75]	125057	1			T2	14		T3	11		T4	9
valid_sources[0x76]	137702	1			T2	19		T4	15		T5	1
valid_sources[0x77]	136524	1			T2	7		T3	18		T4	20
valid_sources[0x78]	118316	1			T1	1		T2	22		T3	3
valid_sources[0x79]	144852	1			T2	7		T3	4		T4	16
valid_sources[0x7a]	123113	1			T1	5		T2	10		T3	1
valid_sources[0x7b]	121733	1			T2	3		T3	1		T4	15
valid_sources[0x7c]	132481	1			T1	3		T2	11		T3	8
valid_sources[0x7d]	131807	1			T2	10		T3	2		T4	29
valid_sources[0x7e]	135897	1			T1	1		T2	11		T3	1
valid_sources[0x7f]	132348	1			T1	1		T2	23		T3	13
valid_sources[0x80]	146519	1			T1	1		T2	10		T3	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

6714349

1

T1

162

T2

730

T3

342

values[0x0]

all_enables

biggest_size

191514

1

T1

16

T2

65

T3

51

values[0x1]

all_enables

biggest_size

133142

1

T1

11

T2

45

T3

62