Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.48	100.00	100.00	93.91			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	374799633	0	0	0
ctrl_rd_A	374799633	2440	0	0
host_fifo_config_rd_A	374799633	3708	0	0
host_nack_handler_timeout_rd_A	374799633	1474	0	0
host_timeout_ctrl_rd_A	374799633	1390	0	0
intr_enable_rd_A	374799633	3874	0	0
ovrd_rd_A	374799633	2276	0	0
target_fifo_config_rd_A	374799633	1401	0	0
target_id_rd_A	374799633	1905	0	0
target_timeout_ctrl_rd_A	374799633	1465	0	0
timeout_ctrl_rd_A	374799633	1887	0	0
timing0_rd_A	374799633	1549	0	0
timing1_rd_A	374799633	1516	0	0
timing2_rd_A	374799633	1623	0	0
timing3_rd_A	374799633	1557	0	0
timing4_rd_A	374799633	1392	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	374799633	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	374799633	2440	0	0
T88	12686	136	0	0
T89	1851	7	0	0
T90	7794	160	0	0
T91	2836	9	0	0
T92	27328	207	0	0
T93	13328	259	0	0
T94	3980	24	0	0
T95	3223	43	0	0
T96	3012	9	0	0
T97	6391	11	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	374799633	3708	0	0
T16	12769	0	0	0
T18	119674	0	0	0
T27	138256	71	0	0
T39	2361	0	0	0
T40	16300	0	0	0
T63	73414	0	0	0
T64	60797	0	0	0
T65	56940	0	0	0
T66	21097	0	0	0
T98	0	155	0	0
T99	0	183	0	0
T100	0	140	0	0
T101	0	126	0	0
T102	0	179	0	0
T103	0	96	0	0
T104	0	123	0	0
T105	0	189	0	0
T106	0	106	0	0
T107	36426	0	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	374799633	1474	0	0
T88	12686	46	0	0
T89	1851	13	0	0
T90	7794	54	0	0
T91	2836	9	0	0
T92	27328	240	0	0
T93	13328	133	0	0
T94	3980	15	0	0
T95	3223	17	0	0
T96	3012	20	0	0
T108	5572	32	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	374799633	1390	0	0
T88	12686	38	0	0
T89	1851	16	0	0
T90	7794	34	0	0
T91	2836	10	0	0
T92	27328	242	0	0
T93	13328	97	0	0
T94	3980	15	0	0
T95	3223	7	0	0
T96	3012	5	0	0
T97	6391	20	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	374799633	3874	0	0
T16	12769	0	0	0
T18	119674	0	0	0
T27	138256	4	0	0
T39	2361	0	0	0
T40	16300	0	0	0
T63	73414	0	0	0
T64	60797	0	0	0
T65	56940	0	0	0
T66	21097	0	0	0
T88	0	322	0	0
T89	0	12	0	0
T90	0	378	0	0
T91	0	11	0	0
T92	0	221	0	0
T93	0	517	0	0
T94	0	24	0	0
T95	0	80	0	0
T107	36426	0	0	0
T109	0	14	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	374799633	2276	0	0
T23	266396	0	0	0
T110	2770	27	0	0
T111	0	55	0	0
T112	0	51	0	0
T113	0	31	0	0
T114	0	34	0	0
T115	0	57	0	0
T116	0	39	0	0
T117	0	66	0	0
T118	0	19	0	0
T119	0	43	0	0
T120	332928	0	0	0
T121	107311	0	0	0
T122	317570	0	0	0
T123	1893	0	0	0
T124	505010	0	0	0
T125	62854	0	0	0
T126	88039	0	0	0
T127	41262	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	374799633	1401	0	0
T88	12686	52	0	0
T89	1851	6	0	0
T90	7794	55	0	0
T91	2836	12	0	0
T92	27328	212	0	0
T93	13328	73	0	0
T94	3980	8	0	0
T95	3223	15	0	0
T96	3012	11	0	0
T97	6391	22	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	374799633	1905	0	0
T88	12686	85	0	0
T89	1851	7	0	0
T90	7794	121	0	0
T91	2836	11	0	0
T92	27328	196	0	0
T93	13328	195	0	0
T94	3980	57	0	0
T95	3223	16	0	0
T96	3012	6	0	0
T97	6391	21	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	374799633	1465	0	0
T88	12686	58	0	0
T89	1851	4	0	0
T90	7794	40	0	0
T91	2836	6	0	0
T92	27328	232	0	0
T93	13328	91	0	0
T94	3980	22	0	0
T95	3223	37	0	0
T96	3012	30	0	0
T97	6391	2	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	374799633	1887	0	0
T88	12686	79	0	0
T89	1851	6	0	0
T90	7794	66	0	0
T91	2836	4	0	0
T92	27328	220	0	0
T93	13328	202	0	0
T94	3980	27	0	0
T95	3223	21	0	0
T96	3012	25	0	0
T97	6391	11	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	374799633	1549	0	0
T88	12686	47	0	0
T89	1851	20	0	0
T90	7794	72	0	0
T91	2836	13	0	0
T92	27328	205	0	0
T93	13328	98	0	0
T94	3980	32	0	0
T95	3223	24	0	0
T97	6391	7	0	0
T108	5572	33	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	374799633	1516	0	0
T88	12686	82	0	0
T89	1851	13	0	0
T90	7794	48	0	0
T91	2836	2	0	0
T92	27328	221	0	0
T93	13328	151	0	0
T94	3980	6	0	0
T95	3223	17	0	0
T96	3012	22	0	0
T97	6391	23	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	374799633	1623	0	0
T88	12686	73	0	0
T89	1851	13	0	0
T90	7794	72	0	0
T91	2836	9	0	0
T92	27328	218	0	0
T93	13328	114	0	0
T94	3980	33	0	0
T95	3223	15	0	0
T96	3012	1	0	0
T97	6391	11	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	374799633	1557	0	0
T88	12686	46	0	0
T89	1851	6	0	0
T90	7794	76	0	0
T91	2836	10	0	0
T92	27328	231	0	0
T93	13328	83	0	0
T94	3980	28	0	0
T95	3223	22	0	0
T97	6391	10	0	0
T108	5572	34	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	374799633	1392	0	0
T88	12686	32	0	0
T89	1851	8	0	0
T90	7794	69	0	0
T91	2836	14	0	0
T92	27328	207	0	0
T93	13328	97	0	0
T94	3980	22	0	0
T95	3223	13	0	0
T96	3012	14	0	0
T108	5572	25	0	0