Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	263	1			T1	7		T2	4		T3	4
all_values[1]	263	1			T1	7		T2	4		T3	4
all_values[2]	263	1			T1	7		T2	4		T3	4
all_values[3]	263	1			T1	7		T2	4		T3	4
all_values[4]	263	1			T1	7		T2	4		T3	4
all_values[5]	263	1			T1	7		T2	4		T3	4
all_values[6]	263	1			T1	7		T2	4		T3	4
all_values[7]	263	1			T1	7		T2	4		T3	4
all_values[8]	263	1			T1	7		T2	4		T3	4
all_values[9]	263	1			T1	7		T2	4		T3	4
all_values[10]	263	1			T1	7		T2	4		T3	4
all_values[11]	263	1			T1	7		T2	4		T3	4
all_values[12]	263	1			T1	7		T2	4		T3	4
all_values[13]	263	1			T1	7		T2	4		T3	4
all_values[14]	263	1			T1	7		T2	4		T3	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2139

1

T1

58

T2

46

T3

33

auto[1]

1806

1

T1

47

T2

14

T3

27

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

723

1

T1

7

T2

22

T3

16

auto[1]

3222

1

T1

98

T2

38

T3

44

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2346

1

T1

57

T2

41

T3

39

auto[1]

1599

1

T1

48

T2

19

T3

21

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	32	1			T21	1		T27	2		T31	4
all_values[0]	auto[0]	auto[0]	auto[1]	48	1			T2	1		T3	1		T11	2
all_values[0]	auto[0]	auto[1]	auto[0]	17	1			T35	2		T27	2		T34	1
all_values[0]	auto[0]	auto[1]	auto[1]	58	1			T1	2		T2	2		T3	2
all_values[0]	auto[1]	auto[0]	auto[1]	58	1			T1	3		T2	1		T3	1
all_values[0]	auto[1]	auto[1]	auto[1]	50	1			T1	2		T11	2		T12	4
all_values[1]	auto[0]	auto[0]	auto[0]	28	1			T1	1		T11	1		T70	2
all_values[1]	auto[0]	auto[0]	auto[1]	65	1			T1	3		T2	1		T11	2
all_values[1]	auto[0]	auto[1]	auto[0]	8	1			T70	2		T71	2		T72	1
all_values[1]	auto[0]	auto[1]	auto[1]	58	1			T1	1		T2	2		T3	1
all_values[1]	auto[1]	auto[0]	auto[1]	51	1			T1	2		T2	1		T3	1
all_values[1]	auto[1]	auto[1]	auto[1]	53	1			T3	2		T12	2		T21	1
all_values[2]	auto[0]	auto[0]	auto[0]	20	1			T2	1		T3	1		T13	2
all_values[2]	auto[0]	auto[0]	auto[1]	52	1			T1	3		T2	1		T12	1
all_values[2]	auto[0]	auto[1]	auto[0]	18	1			T11	1		T73	1		T74	1
all_values[2]	auto[0]	auto[1]	auto[1]	62	1			T1	2		T3	1		T11	2
all_values[2]	auto[1]	auto[0]	auto[1]	61	1			T1	2		T2	2		T3	1
all_values[2]	auto[1]	auto[1]	auto[1]	50	1			T3	1		T11	3		T12	1
all_values[3]	auto[0]	auto[0]	auto[0]	30	1			T27	2		T31	2		T34	1
all_values[3]	auto[0]	auto[0]	auto[1]	63	1			T1	5		T2	1		T3	1
all_values[3]	auto[0]	auto[1]	auto[0]	19	1			T13	1		T70	3		T52	3
all_values[3]	auto[0]	auto[1]	auto[1]	47	1			T3	1		T11	1		T12	1
all_values[3]	auto[1]	auto[0]	auto[1]	52	1			T1	1		T2	3		T3	1
all_values[3]	auto[1]	auto[1]	auto[1]	52	1			T1	1		T3	1		T11	1
all_values[4]	auto[0]	auto[0]	auto[0]	24	1			T3	1		T34	1		T52	3
all_values[4]	auto[0]	auto[0]	auto[1]	68	1			T1	1		T3	1		T11	3
all_values[4]	auto[0]	auto[1]	auto[0]	12	1			T35	1		T31	1		T73	1
all_values[4]	auto[0]	auto[1]	auto[1]	59	1			T1	1		T2	2		T3	1
all_values[4]	auto[1]	auto[0]	auto[1]	58	1			T1	2		T2	1		T11	3
all_values[4]	auto[1]	auto[1]	auto[1]	42	1			T1	3		T2	1		T3	1
all_values[5]	auto[0]	auto[0]	auto[0]	30	1			T1	1		T2	4		T3	1
all_values[5]	auto[0]	auto[0]	auto[1]	54	1			T1	3		T3	1		T12	1
all_values[5]	auto[0]	auto[1]	auto[0]	25	1			T11	1		T12	2		T70	2
all_values[5]	auto[0]	auto[1]	auto[1]	42	1			T1	1		T11	3		T12	1
all_values[5]	auto[1]	auto[0]	auto[1]	69	1			T1	1		T11	1		T12	1
all_values[5]	auto[1]	auto[1]	auto[1]	43	1			T1	1		T3	2		T11	1
all_values[6]	auto[0]	auto[0]	auto[0]	33	1			T1	1		T12	1		T21	1
all_values[6]	auto[0]	auto[0]	auto[1]	63	1			T1	1		T2	1		T3	1
all_values[6]	auto[0]	auto[1]	auto[0]	21	1			T1	1		T13	2		T52	1
all_values[6]	auto[0]	auto[1]	auto[1]	44	1			T1	2		T2	2		T3	1
all_values[6]	auto[1]	auto[0]	auto[1]	66	1			T1	1		T2	1		T3	2
all_values[6]	auto[1]	auto[1]	auto[1]	36	1			T1	1		T12	1		T35	2
all_values[7]	auto[0]	auto[0]	auto[0]	30	1			T1	1		T2	4		T11	4
all_values[7]	auto[0]	auto[0]	auto[1]	56	1			T1	2		T12	2		T13	1
all_values[7]	auto[0]	auto[1]	auto[0]	14	1			T11	1		T27	2		T52	1
all_values[7]	auto[0]	auto[1]	auto[1]	47	1			T1	2		T3	2		T11	1
all_values[7]	auto[1]	auto[0]	auto[1]	68	1			T1	1		T3	2		T11	1
all_values[7]	auto[1]	auto[1]	auto[1]	48	1			T1	1		T12	3		T21	1
all_values[8]	auto[0]	auto[0]	auto[0]	40	1			T3	2		T13	1		T34	1
all_values[8]	auto[0]	auto[0]	auto[1]	45	1			T1	3		T2	2		T12	1
all_values[8]	auto[0]	auto[1]	auto[0]	27	1			T11	1		T34	3		T52	2
all_values[8]	auto[0]	auto[1]	auto[1]	54	1			T1	1		T3	1		T11	2
all_values[8]	auto[1]	auto[0]	auto[1]	51	1			T1	2		T2	2		T3	1
all_values[8]	auto[1]	auto[1]	auto[1]	46	1			T1	1		T11	3		T12	1
all_values[9]	auto[0]	auto[0]	auto[0]	36	1			T2	4		T3	1		T12	2
all_values[9]	auto[0]	auto[0]	auto[1]	46	1			T1	1		T3	1		T11	1
all_values[9]	auto[0]	auto[1]	auto[0]	14	1			T13	1		T31	2		T75	1
all_values[9]	auto[0]	auto[1]	auto[1]	55	1			T1	1		T3	1		T11	2
all_values[9]	auto[1]	auto[0]	auto[1]	66	1			T1	3		T3	1		T11	2
all_values[9]	auto[1]	auto[1]	auto[1]	46	1			T1	2		T11	2		T12	1
all_values[10]	auto[0]	auto[0]	auto[0]	31	1			T1	1		T12	3		T21	1
all_values[10]	auto[0]	auto[0]	auto[1]	47	1			T2	1		T3	1		T11	3
all_values[10]	auto[0]	auto[1]	auto[0]	19	1			T27	4		T31	4		T71	3
all_values[10]	auto[0]	auto[1]	auto[1]	62	1			T1	2		T3	2		T11	2
all_values[10]	auto[1]	auto[0]	auto[1]	52	1			T1	1		T2	3		T3	1
all_values[10]	auto[1]	auto[1]	auto[1]	52	1			T1	3		T11	1		T13	2
all_values[11]	auto[0]	auto[0]	auto[0]	20	1			T3	1		T12	1		T13	1
all_values[11]	auto[0]	auto[0]	auto[1]	52	1			T1	2		T2	1		T11	4
all_values[11]	auto[0]	auto[1]	auto[0]	21	1			T27	4		T52	1		T73	3
all_values[11]	auto[0]	auto[1]	auto[1]	59	1			T1	1		T2	1		T3	1
all_values[11]	auto[1]	auto[0]	auto[1]	62	1			T1	2		T2	2		T3	1
all_values[11]	auto[1]	auto[1]	auto[1]	49	1			T1	2		T3	1		T11	1
all_values[12]	auto[0]	auto[0]	auto[0]	33	1			T1	1		T2	4		T3	2
all_values[12]	auto[0]	auto[0]	auto[1]	48	1			T1	1		T12	2		T35	2
all_values[12]	auto[0]	auto[1]	auto[0]	29	1			T3	2		T12	2		T13	4
all_values[12]	auto[0]	auto[1]	auto[1]	58	1			T1	2		T11	4		T21	1
all_values[12]	auto[1]	auto[0]	auto[1]	42	1			T27	2		T31	1		T70	1
all_values[12]	auto[1]	auto[1]	auto[1]	53	1			T1	3		T11	2		T12	3
all_values[13]	auto[0]	auto[0]	auto[0]	24	1			T2	1		T3	1		T21	2
all_values[13]	auto[0]	auto[0]	auto[1]	54	1			T1	1		T3	1		T11	1
all_values[13]	auto[0]	auto[1]	auto[0]	23	1			T35	2		T70	1		T52	3
all_values[13]	auto[0]	auto[1]	auto[1]	50	1			T1	3		T2	1		T3	1
all_values[13]	auto[1]	auto[0]	auto[1]	65	1			T1	2		T2	2		T3	1
all_values[13]	auto[1]	auto[1]	auto[1]	47	1			T1	1		T11	2		T12	3
all_values[14]	auto[0]	auto[0]	auto[0]	28	1			T2	1		T3	2		T11	1
all_values[14]	auto[0]	auto[0]	auto[1]	56	1			T11	3		T12	3		T35	1
all_values[14]	auto[0]	auto[1]	auto[0]	17	1			T2	3		T3	2		T13	1
all_values[14]	auto[0]	auto[1]	auto[1]	51	1			T1	3		T11	1		T12	2
all_values[14]	auto[1]	auto[0]	auto[1]	62	1			T1	3		T11	1		T12	2
all_values[14]	auto[1]	auto[1]	auto[1]	49	1			T1	1		T11	1		T13	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal