| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 52.69 | 40.66 | 40.76 | 90.72 | 0.00 | 42.98 | 99.68 | 54.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP | |||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 46.04 | 46.04 | 39.00 | 39.00 | 36.81 | 36.81 | 93.30 | 93.30 | 0.00 | 0.00 | 41.70 | 41.70 | 95.54 | 95.54 | 15.89 | 15.89 | /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.3183116836 |
| 51.01 | 4.98 | 40.20 | 1.19 | 38.99 | 2.18 | 96.28 | 2.98 | 0.00 | 0.00 | 42.91 | 1.21 | 95.86 | 0.32 | 42.84 | 26.95 | /workspace/coverage/cover_reg_top/6.i2c_intr_test.583652620 |
| 52.00 | 0.99 | 40.20 | 0.00 | 40.16 | 1.17 | 96.77 | 0.50 | 0.00 | 0.00 | 42.98 | 0.07 | 96.82 | 0.96 | 47.05 | 4.21 | /workspace/coverage/cover_reg_top/4.i2c_tl_errors.4227739613 |
| 52.47 | 0.47 | 40.20 | 0.00 | 40.16 | 0.00 | 97.02 | 0.25 | 0.00 | 0.00 | 42.98 | 0.00 | 96.82 | 0.00 | 50.11 | 3.05 | /workspace/coverage/cover_reg_top/4.i2c_intr_test.334427488 |
| 52.92 | 0.45 | 40.20 | 0.00 | 40.16 | 0.00 | 97.02 | 0.00 | 0.00 | 0.00 | 42.98 | 0.00 | 99.68 | 2.87 | 50.42 | 0.32 | /workspace/coverage/cover_reg_top/12.i2c_csr_rw.2794693492 |
| 53.05 | 0.13 | 40.66 | 0.46 | 40.27 | 0.11 | 97.02 | 0.00 | 0.00 | 0.00 | 42.98 | 0.00 | 99.68 | 0.00 | 50.74 | 0.32 | /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.1353061344 |
| 53.17 | 0.12 | 40.66 | 0.00 | 40.27 | 0.00 | 97.02 | 0.00 | 0.00 | 0.00 | 42.98 | 0.00 | 99.68 | 0.00 | 51.58 | 0.84 | /workspace/coverage/cover_reg_top/15.i2c_intr_test.2959887739 |
| 53.26 | 0.09 | 40.66 | 0.00 | 40.50 | 0.23 | 97.02 | 0.00 | 0.00 | 0.00 | 42.98 | 0.00 | 99.68 | 0.00 | 52.00 | 0.42 | /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.2942188948 |
| 53.34 | 0.08 | 40.66 | 0.00 | 40.50 | 0.00 | 97.02 | 0.00 | 0.00 | 0.00 | 42.98 | 0.00 | 99.68 | 0.00 | 52.53 | 0.53 | /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.51661450 |
| 53.41 | 0.08 | 40.66 | 0.00 | 40.50 | 0.00 | 97.02 | 0.00 | 0.00 | 0.00 | 42.98 | 0.00 | 99.68 | 0.00 | 53.05 | 0.53 | /workspace/coverage/cover_reg_top/20.i2c_intr_test.1922535590 |
| 53.46 | 0.05 | 40.66 | 0.00 | 40.50 | 0.00 | 97.02 | 0.00 | 0.00 | 0.00 | 42.98 | 0.00 | 99.68 | 0.00 | 53.37 | 0.32 | /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.346718866 |
| 53.49 | 0.03 | 40.66 | 0.00 | 40.50 | 0.00 | 97.02 | 0.00 | 0.00 | 0.00 | 42.98 | 0.00 | 99.68 | 0.00 | 53.58 | 0.21 | /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.2328522952 |
| 53.52 | 0.03 | 40.66 | 0.00 | 40.50 | 0.00 | 97.02 | 0.00 | 0.00 | 0.00 | 42.98 | 0.00 | 99.68 | 0.00 | 53.79 | 0.21 | /workspace/coverage/cover_reg_top/27.i2c_intr_test.4221458279 |
| 53.54 | 0.02 | 40.66 | 0.00 | 40.53 | 0.04 | 97.02 | 0.00 | 0.00 | 0.00 | 42.98 | 0.00 | 99.68 | 0.00 | 53.89 | 0.11 | /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.1468690371 |
| 53.55 | 0.02 | 40.66 | 0.00 | 40.65 | 0.11 | 97.02 | 0.00 | 0.00 | 0.00 | 42.98 | 0.00 | 99.68 | 0.00 | 53.89 | 0.00 | /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.4098090786 |
| 53.57 | 0.02 | 40.66 | 0.00 | 40.65 | 0.00 | 97.02 | 0.00 | 0.00 | 0.00 | 42.98 | 0.00 | 99.68 | 0.00 | 54.00 | 0.11 | /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.459766925 |
| 53.57 | 0.01 | 40.66 | 0.00 | 40.68 | 0.04 | 97.02 | 0.00 | 0.00 | 0.00 | 42.98 | 0.00 | 99.68 | 0.00 | 54.00 | 0.00 | /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.73710776 |
| 53.58 | 0.01 | 40.66 | 0.00 | 40.72 | 0.04 | 97.02 | 0.00 | 0.00 | 0.00 | 42.98 | 0.00 | 99.68 | 0.00 | 54.00 | 0.00 | /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.4128054225 |
| 53.59 | 0.01 | 40.66 | 0.00 | 40.76 | 0.04 | 97.02 | 0.00 | 0.00 | 0.00 | 42.98 | 0.00 | 99.68 | 0.00 | 54.00 | 0.00 | /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.2501590152 |
| Name |
|---|
| /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.3251638592 |
| /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.4259775569 |
| /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.3462022502 |
| /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.256442005 |
| /workspace/coverage/cover_reg_top/0.i2c_csr_rw.2561676595 |
| /workspace/coverage/cover_reg_top/0.i2c_intr_test.2586343278 |
| /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.1259972311 |
| /workspace/coverage/cover_reg_top/0.i2c_tl_errors.525236622 |
| /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.729543865 |
| /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.3581030233 |
| /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.3549483019 |
| /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.897128538 |
| /workspace/coverage/cover_reg_top/1.i2c_csr_rw.521065251 |
| /workspace/coverage/cover_reg_top/1.i2c_intr_test.2505879719 |
| /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.1885117022 |
| /workspace/coverage/cover_reg_top/1.i2c_tl_errors.3227870939 |
| /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.1360255637 |
| /workspace/coverage/cover_reg_top/10.i2c_csr_rw.230159184 |
| /workspace/coverage/cover_reg_top/10.i2c_intr_test.3852217087 |
| /workspace/coverage/cover_reg_top/10.i2c_tl_errors.449674543 |
| /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.347203608 |
| /workspace/coverage/cover_reg_top/11.i2c_csr_rw.2788483119 |
| /workspace/coverage/cover_reg_top/11.i2c_intr_test.4122593689 |
| /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.2406413669 |
| /workspace/coverage/cover_reg_top/11.i2c_tl_errors.1714995191 |
| /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.1635156486 |
| /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.3859503252 |
| /workspace/coverage/cover_reg_top/12.i2c_intr_test.2473127564 |
| /workspace/coverage/cover_reg_top/12.i2c_tl_errors.4286621754 |
| /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.3267170181 |
| /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.604299314 |
| /workspace/coverage/cover_reg_top/13.i2c_csr_rw.564277265 |
| /workspace/coverage/cover_reg_top/13.i2c_intr_test.1809562801 |
| /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.954803469 |
| /workspace/coverage/cover_reg_top/13.i2c_tl_errors.1460360709 |
| /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.3652088359 |
| /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.1335931367 |
| /workspace/coverage/cover_reg_top/14.i2c_csr_rw.4151364999 |
| /workspace/coverage/cover_reg_top/14.i2c_intr_test.1890636588 |
| /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.500062585 |
| /workspace/coverage/cover_reg_top/14.i2c_tl_errors.1906509204 |
| /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.1878934458 |
| /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.1169228485 |
| /workspace/coverage/cover_reg_top/15.i2c_csr_rw.3055051011 |
| /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.1738580541 |
| /workspace/coverage/cover_reg_top/15.i2c_tl_errors.2297148735 |
| /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.3076794342 |
| /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.4028776030 |
| /workspace/coverage/cover_reg_top/16.i2c_csr_rw.3920564573 |
| /workspace/coverage/cover_reg_top/16.i2c_intr_test.4244650234 |
| /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.4124997032 |
| /workspace/coverage/cover_reg_top/16.i2c_tl_errors.501779073 |
| /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.3779203925 |
| /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.3568486177 |
| /workspace/coverage/cover_reg_top/17.i2c_csr_rw.2285173829 |
| /workspace/coverage/cover_reg_top/17.i2c_intr_test.4115309727 |
| /workspace/coverage/cover_reg_top/17.i2c_tl_errors.2362274390 |
| /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.3113061723 |
| /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.2967520938 |
| /workspace/coverage/cover_reg_top/18.i2c_csr_rw.1259750088 |
| /workspace/coverage/cover_reg_top/18.i2c_intr_test.931130069 |
| /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.1655872252 |
| /workspace/coverage/cover_reg_top/18.i2c_tl_errors.455626987 |
| /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.2254713210 |
| /workspace/coverage/cover_reg_top/19.i2c_csr_rw.807039165 |
| /workspace/coverage/cover_reg_top/19.i2c_intr_test.1726502021 |
| /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.3428901767 |
| /workspace/coverage/cover_reg_top/19.i2c_tl_errors.2911910888 |
| /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.849370500 |
| /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.2844053578 |
| /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.1728610859 |
| /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.1257408639 |
| /workspace/coverage/cover_reg_top/2.i2c_csr_rw.3202668760 |
| /workspace/coverage/cover_reg_top/2.i2c_intr_test.1578856983 |
| /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.4222407613 |
| /workspace/coverage/cover_reg_top/2.i2c_tl_errors.2320851260 |
| /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.2540410013 |
| /workspace/coverage/cover_reg_top/21.i2c_intr_test.3175073125 |
| /workspace/coverage/cover_reg_top/22.i2c_intr_test.377536181 |
| /workspace/coverage/cover_reg_top/23.i2c_intr_test.1697829739 |
| /workspace/coverage/cover_reg_top/24.i2c_intr_test.1840808038 |
| /workspace/coverage/cover_reg_top/25.i2c_intr_test.328982884 |
| /workspace/coverage/cover_reg_top/26.i2c_intr_test.2582587931 |
| /workspace/coverage/cover_reg_top/28.i2c_intr_test.1310968424 |
| /workspace/coverage/cover_reg_top/29.i2c_intr_test.3755936785 |
| /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.1069061941 |
| /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.1921572398 |
| /workspace/coverage/cover_reg_top/3.i2c_csr_rw.1040497970 |
| /workspace/coverage/cover_reg_top/3.i2c_intr_test.3713817938 |
| /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.3663266943 |
| /workspace/coverage/cover_reg_top/3.i2c_tl_errors.2887028674 |
| /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.3821852649 |
| /workspace/coverage/cover_reg_top/30.i2c_intr_test.1331953813 |
| /workspace/coverage/cover_reg_top/31.i2c_intr_test.3450467521 |
| /workspace/coverage/cover_reg_top/32.i2c_intr_test.721463897 |
| /workspace/coverage/cover_reg_top/33.i2c_intr_test.626422394 |
| /workspace/coverage/cover_reg_top/34.i2c_intr_test.4214437604 |
| /workspace/coverage/cover_reg_top/35.i2c_intr_test.1266946590 |
| /workspace/coverage/cover_reg_top/36.i2c_intr_test.1670783137 |
| /workspace/coverage/cover_reg_top/37.i2c_intr_test.159019811 |
| /workspace/coverage/cover_reg_top/38.i2c_intr_test.1815555281 |
| /workspace/coverage/cover_reg_top/39.i2c_intr_test.620796627 |
| /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.1011729106 |
| /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.1165319296 |
| /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.3492988243 |
| /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.1636590372 |
| /workspace/coverage/cover_reg_top/4.i2c_csr_rw.342510811 |
| /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.3253395035 |
| /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.775791716 |
| /workspace/coverage/cover_reg_top/40.i2c_intr_test.1779353837 |
| /workspace/coverage/cover_reg_top/41.i2c_intr_test.1120812918 |
| /workspace/coverage/cover_reg_top/42.i2c_intr_test.1802855784 |
| /workspace/coverage/cover_reg_top/43.i2c_intr_test.2274529711 |
| /workspace/coverage/cover_reg_top/44.i2c_intr_test.2995971271 |
| /workspace/coverage/cover_reg_top/45.i2c_intr_test.937803084 |
| /workspace/coverage/cover_reg_top/46.i2c_intr_test.4259893656 |
| /workspace/coverage/cover_reg_top/47.i2c_intr_test.101879770 |
| /workspace/coverage/cover_reg_top/48.i2c_intr_test.3699349600 |
| /workspace/coverage/cover_reg_top/49.i2c_intr_test.1433153919 |
| /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.2246826941 |
| /workspace/coverage/cover_reg_top/5.i2c_csr_rw.528518651 |
| /workspace/coverage/cover_reg_top/5.i2c_intr_test.1872551195 |
| /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.2654537870 |
| /workspace/coverage/cover_reg_top/5.i2c_tl_errors.406203123 |
| /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.680846208 |
| /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.12550967 |
| /workspace/coverage/cover_reg_top/6.i2c_csr_rw.3255354860 |
| /workspace/coverage/cover_reg_top/6.i2c_tl_errors.4090027035 |
| /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.4169409330 |
| /workspace/coverage/cover_reg_top/7.i2c_csr_rw.1151266172 |
| /workspace/coverage/cover_reg_top/7.i2c_intr_test.62485910 |
| /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.1123298573 |
| /workspace/coverage/cover_reg_top/7.i2c_tl_errors.1033906058 |
| /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.720946901 |
| /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.1754465478 |
| /workspace/coverage/cover_reg_top/8.i2c_csr_rw.3054241116 |
| /workspace/coverage/cover_reg_top/8.i2c_intr_test.2226486158 |
| /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.1125205558 |
| /workspace/coverage/cover_reg_top/8.i2c_tl_errors.2290656157 |
| /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.504473519 |
| /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.1335585032 |
| /workspace/coverage/cover_reg_top/9.i2c_csr_rw.3366659754 |
| /workspace/coverage/cover_reg_top/9.i2c_intr_test.674896863 |
| /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.758803629 |
| /workspace/coverage/cover_reg_top/9.i2c_tl_errors.4031878749 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/cover_reg_top/44.i2c_intr_test.2995971271 | Jul 19 04:30:52 PM PDT 24 | Jul 19 04:31:06 PM PDT 24 | 18830995 ps | ||
| T2 | /workspace/coverage/cover_reg_top/5.i2c_intr_test.1872551195 | Jul 19 04:30:27 PM PDT 24 | Jul 19 04:30:31 PM PDT 24 | 22760716 ps | ||
| T3 | /workspace/coverage/cover_reg_top/42.i2c_intr_test.1802855784 | Jul 19 04:30:50 PM PDT 24 | Jul 19 04:30:57 PM PDT 24 | 24350909 ps | ||
| T4 | /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.3183116836 | Jul 19 04:30:54 PM PDT 24 | Jul 19 04:31:11 PM PDT 24 | 259425413 ps | ||
| T7 | /workspace/coverage/cover_reg_top/6.i2c_csr_rw.3255354860 | Jul 19 04:30:25 PM PDT 24 | Jul 19 04:30:29 PM PDT 24 | 55940856 ps | ||
| T5 | /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.3253395035 | Jul 19 04:30:28 PM PDT 24 | Jul 19 04:30:32 PM PDT 24 | 176700975 ps | ||
| T11 | /workspace/coverage/cover_reg_top/6.i2c_intr_test.583652620 | Jul 19 04:30:26 PM PDT 24 | Jul 19 04:30:30 PM PDT 24 | 15156927 ps | ||
| T10 | /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.1259972311 | Jul 19 04:30:10 PM PDT 24 | Jul 19 04:30:20 PM PDT 24 | 22731601 ps | ||
| T12 | /workspace/coverage/cover_reg_top/34.i2c_intr_test.4214437604 | Jul 19 04:30:52 PM PDT 24 | Jul 19 04:31:06 PM PDT 24 | 26542868 ps | ||
| T13 | /workspace/coverage/cover_reg_top/18.i2c_intr_test.931130069 | Jul 19 04:30:50 PM PDT 24 | Jul 19 04:31:01 PM PDT 24 | 15982933 ps | ||
| T21 | /workspace/coverage/cover_reg_top/28.i2c_intr_test.1310968424 | Jul 19 04:30:50 PM PDT 24 | Jul 19 04:31:01 PM PDT 24 | 47489280 ps | ||
| T6 | /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.1728610859 | Jul 19 04:30:21 PM PDT 24 | Jul 19 04:30:26 PM PDT 24 | 34697721 ps | ||
| T22 | /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.51661450 | Jul 19 04:30:39 PM PDT 24 | Jul 19 04:30:45 PM PDT 24 | 162946447 ps | ||
| T35 | /workspace/coverage/cover_reg_top/1.i2c_intr_test.2505879719 | Jul 19 04:30:19 PM PDT 24 | Jul 19 04:30:25 PM PDT 24 | 19646427 ps | ||
| T8 | /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.729543865 | Jul 19 04:30:09 PM PDT 24 | Jul 19 04:30:21 PM PDT 24 | 46167479 ps | ||
| T26 | /workspace/coverage/cover_reg_top/12.i2c_csr_rw.2794693492 | Jul 19 04:30:38 PM PDT 24 | Jul 19 04:30:42 PM PDT 24 | 25486090 ps | ||
| T9 | /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.1754465478 | Jul 19 04:30:36 PM PDT 24 | Jul 19 04:30:39 PM PDT 24 | 30236685 ps | ||
| T27 | /workspace/coverage/cover_reg_top/16.i2c_intr_test.4244650234 | Jul 19 04:30:43 PM PDT 24 | Jul 19 04:30:48 PM PDT 24 | 26798828 ps | ||
| T28 | /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.2844053578 | Jul 19 04:30:20 PM PDT 24 | Jul 19 04:30:28 PM PDT 24 | 1089459695 ps | ||
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| T144 | /workspace/coverage/cover_reg_top/6.i2c_tl_errors.4090027035 | Jul 19 04:30:26 PM PDT 24 | Jul 19 04:30:31 PM PDT 24 | 48983604 ps | ||
| T145 | /workspace/coverage/cover_reg_top/49.i2c_intr_test.1433153919 | Jul 19 04:30:54 PM PDT 24 | Jul 19 04:31:10 PM PDT 24 | 177236800 ps | ||
| T146 | /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.4028776030 | Jul 19 04:30:37 PM PDT 24 | Jul 19 04:30:40 PM PDT 24 | 41035996 ps | ||
| T147 | /workspace/coverage/cover_reg_top/8.i2c_intr_test.2226486158 | Jul 19 04:30:35 PM PDT 24 | Jul 19 04:30:36 PM PDT 24 | 53722112 ps | ||
| T148 | /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.758803629 | Jul 19 04:30:39 PM PDT 24 | Jul 19 04:30:44 PM PDT 24 | 205612620 ps | ||
| T149 | /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.3549483019 | Jul 19 04:30:17 PM PDT 24 | Jul 19 04:30:27 PM PDT 24 | 909200430 ps | ||
| T150 | /workspace/coverage/cover_reg_top/48.i2c_intr_test.3699349600 | Jul 19 04:30:49 PM PDT 24 | Jul 19 04:30:54 PM PDT 24 | 31435550 ps | ||
| T151 | /workspace/coverage/cover_reg_top/41.i2c_intr_test.1120812918 | Jul 19 04:30:54 PM PDT 24 | Jul 19 04:31:09 PM PDT 24 | 30311679 ps | ||
| T152 | /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.3251638592 | Jul 19 04:30:09 PM PDT 24 | Jul 19 04:30:20 PM PDT 24 | 73448767 ps | ||
| T153 | /workspace/coverage/cover_reg_top/19.i2c_intr_test.1726502021 | Jul 19 04:30:50 PM PDT 24 | Jul 19 04:30:58 PM PDT 24 | 18412613 ps | ||
| T154 | /workspace/coverage/cover_reg_top/12.i2c_tl_errors.4286621754 | Jul 19 04:30:38 PM PDT 24 | Jul 19 04:30:44 PM PDT 24 | 99079064 ps | ||
| T155 | /workspace/coverage/cover_reg_top/39.i2c_intr_test.620796627 | Jul 19 04:30:53 PM PDT 24 | Jul 19 04:31:08 PM PDT 24 | 32815572 ps | ||
| T156 | /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.2654537870 | Jul 19 04:30:30 PM PDT 24 | Jul 19 04:30:33 PM PDT 24 | 163917492 ps | ||
| T157 | /workspace/coverage/cover_reg_top/2.i2c_intr_test.1578856983 | Jul 19 04:30:21 PM PDT 24 | Jul 19 04:30:26 PM PDT 24 | 35518804 ps | ||
| T158 | /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.1360255637 | Jul 19 04:30:37 PM PDT 24 | Jul 19 04:30:40 PM PDT 24 | 109210559 ps | ||
| T159 | /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.3568486177 | Jul 19 04:30:40 PM PDT 24 | Jul 19 04:30:47 PM PDT 24 | 151301218 ps | ||
| T160 | /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.347203608 | Jul 19 04:30:39 PM PDT 24 | Jul 19 04:30:45 PM PDT 24 | 31075344 ps | ||
| T161 | /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.3428901767 | Jul 19 04:30:54 PM PDT 24 | Jul 19 04:31:10 PM PDT 24 | 33215127 ps | ||
| T162 | /workspace/coverage/cover_reg_top/33.i2c_intr_test.626422394 | Jul 19 04:30:52 PM PDT 24 | Jul 19 04:31:06 PM PDT 24 | 19392514 ps | ||
| T50 | /workspace/coverage/cover_reg_top/8.i2c_csr_rw.3054241116 | Jul 19 04:30:40 PM PDT 24 | Jul 19 04:30:46 PM PDT 24 | 28334839 ps | ||
| T49 | /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.1011729106 | Jul 19 04:30:28 PM PDT 24 | Jul 19 04:30:33 PM PDT 24 | 441976645 ps | ||
| T163 | /workspace/coverage/cover_reg_top/24.i2c_intr_test.1840808038 | Jul 19 04:30:55 PM PDT 24 | Jul 19 04:31:12 PM PDT 24 | 40839613 ps | ||
| T164 | /workspace/coverage/cover_reg_top/10.i2c_csr_rw.230159184 | Jul 19 04:30:38 PM PDT 24 | Jul 19 04:30:42 PM PDT 24 | 183258173 ps |
| Test location | /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.3183116836 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 259425413 ps |
| CPU time | 1.48 seconds |
| Started | Jul 19 04:30:54 PM PDT 24 |
| Finished | Jul 19 04:31:11 PM PDT 24 |
| Peak memory | 204380 kb |
| Host | smart-eaefab97-0206-415d-be69-88d958178e0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183116836 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_intg_err.3183116836 |
| Directory | /workspace/19.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/6.i2c_intr_test.583652620 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 15156927 ps |
| CPU time | 0.67 seconds |
| Started | Jul 19 04:30:26 PM PDT 24 |
| Finished | Jul 19 04:30:30 PM PDT 24 |
| Peak memory | 204308 kb |
| Host | smart-e5b91670-1698-42f4-a984-9c13a95c92ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583652620 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_intr_test.583652620 |
| Directory | /workspace/6.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.i2c_tl_errors.4227739613 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 222171389 ps |
| CPU time | 2.22 seconds |
| Started | Jul 19 04:30:27 PM PDT 24 |
| Finished | Jul 19 04:30:32 PM PDT 24 |
| Peak memory | 204432 kb |
| Host | smart-4cb7dcaf-682c-468d-ba01-2c2fd7263be5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227739613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_errors.4227739613 |
| Directory | /workspace/4.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/4.i2c_intr_test.334427488 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 44364340 ps |
| CPU time | 0.67 seconds |
| Started | Jul 19 04:30:27 PM PDT 24 |
| Finished | Jul 19 04:30:30 PM PDT 24 |
| Peak memory | 204256 kb |
| Host | smart-d0213580-d881-4bd1-8103-8be3a32a81c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334427488 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_intr_test.334427488 |
| Directory | /workspace/4.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/12.i2c_csr_rw.2794693492 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 25486090 ps |
| CPU time | 0.75 seconds |
| Started | Jul 19 04:30:38 PM PDT 24 |
| Finished | Jul 19 04:30:42 PM PDT 24 |
| Peak memory | 204276 kb |
| Host | smart-3a6dd0a5-abc6-40c8-af65-2c7e35093a2a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794693492 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_rw.2794693492 |
| Directory | /workspace/12.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.1353061344 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 117046931 ps |
| CPU time | 0.99 seconds |
| Started | Jul 19 04:30:25 PM PDT 24 |
| Finished | Jul 19 04:30:29 PM PDT 24 |
| Peak memory | 204356 kb |
| Host | smart-2317182e-4fd3-4b7c-b2f8-11a035fef1c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353061344 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 3.i2c_csr_mem_rw_with_rand_reset.1353061344 |
| Directory | /workspace/3.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.i2c_intr_test.2959887739 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 22595576 ps |
| CPU time | 0.64 seconds |
| Started | Jul 19 04:30:40 PM PDT 24 |
| Finished | Jul 19 04:30:46 PM PDT 24 |
| Peak memory | 204296 kb |
| Host | smart-b1ca85a4-7697-48fa-9569-d896aba3b079 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959887739 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_intr_test.2959887739 |
| Directory | /workspace/15.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.2942188948 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 118932942 ps |
| CPU time | 2.22 seconds |
| Started | Jul 19 04:30:50 PM PDT 24 |
| Finished | Jul 19 04:31:00 PM PDT 24 |
| Peak memory | 204672 kb |
| Host | smart-130a90a4-7898-4118-bdf4-88a74777ad90 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942188948 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_intg_err.2942188948 |
| Directory | /workspace/18.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.51661450 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 162946447 ps |
| CPU time | 1.08 seconds |
| Started | Jul 19 04:30:39 PM PDT 24 |
| Finished | Jul 19 04:30:45 PM PDT 24 |
| Peak memory | 204460 kb |
| Host | smart-fe3d0f01-f32f-45a3-ad23-64fa57b8cad1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51661450 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_same_csr_out standing.51661450 |
| Directory | /workspace/10.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/20.i2c_intr_test.1922535590 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 28602153 ps |
| CPU time | 0.8 seconds |
| Started | Jul 19 04:30:50 PM PDT 24 |
| Finished | Jul 19 04:31:01 PM PDT 24 |
| Peak memory | 204312 kb |
| Host | smart-2c9083bb-3809-4de0-af6e-8561c163ee31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922535590 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.i2c_intr_test.1922535590 |
| Directory | /workspace/20.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.346718866 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 41693115 ps |
| CPU time | 0.9 seconds |
| Started | Jul 19 04:30:38 PM PDT 24 |
| Finished | Jul 19 04:30:43 PM PDT 24 |
| Peak memory | 204380 kb |
| Host | smart-3ca9c224-49c0-4223-b28c-cdb02da4d1b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346718866 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_same_csr_ou tstanding.346718866 |
| Directory | /workspace/17.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.2328522952 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 45232069 ps |
| CPU time | 0.69 seconds |
| Started | Jul 19 04:30:20 PM PDT 24 |
| Finished | Jul 19 04:30:26 PM PDT 24 |
| Peak memory | 204336 kb |
| Host | smart-1982cf0e-3517-422b-adea-476ba70e30c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328522952 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_hw_reset.2328522952 |
| Directory | /workspace/1.i2c_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/27.i2c_intr_test.4221458279 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 50195287 ps |
| CPU time | 0.66 seconds |
| Started | Jul 19 04:30:55 PM PDT 24 |
| Finished | Jul 19 04:31:13 PM PDT 24 |
| Peak memory | 204300 kb |
| Host | smart-6e1c399a-8482-4b6a-bf78-0b6c656065ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221458279 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.i2c_intr_test.4221458279 |
| Directory | /workspace/27.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.1468690371 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 25996556 ps |
| CPU time | 1.02 seconds |
| Started | Jul 19 04:30:27 PM PDT 24 |
| Finished | Jul 19 04:30:31 PM PDT 24 |
| Peak memory | 204468 kb |
| Host | smart-c29adb6c-6773-4056-b1ae-a63630eb0843 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468690371 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_same_csr_ou tstanding.1468690371 |
| Directory | /workspace/6.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.4098090786 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 337135251 ps |
| CPU time | 2.13 seconds |
| Started | Jul 19 04:30:32 PM PDT 24 |
| Finished | Jul 19 04:30:36 PM PDT 24 |
| Peak memory | 204428 kb |
| Host | smart-04c7e45a-5697-4a24-bd61-40aed2d38810 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098090786 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_intg_err.4098090786 |
| Directory | /workspace/6.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.459766925 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 55361413 ps |
| CPU time | 0.74 seconds |
| Started | Jul 19 04:30:30 PM PDT 24 |
| Finished | Jul 19 04:30:33 PM PDT 24 |
| Peak memory | 204244 kb |
| Host | smart-bb658819-33bc-4418-8e0d-3e5bb3e8bf18 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459766925 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_hw_reset.459766925 |
| Directory | /workspace/3.i2c_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.73710776 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 102528657 ps |
| CPU time | 1.33 seconds |
| Started | Jul 19 04:30:19 PM PDT 24 |
| Finished | Jul 19 04:30:26 PM PDT 24 |
| Peak memory | 204376 kb |
| Host | smart-bbb54dae-3fb1-4495-94d4-e6fb7a39827f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73710776 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_intg_err.73710776 |
| Directory | /workspace/1.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.4128054225 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 96945260 ps |
| CPU time | 2.06 seconds |
| Started | Jul 19 04:30:41 PM PDT 24 |
| Finished | Jul 19 04:30:48 PM PDT 24 |
| Peak memory | 204440 kb |
| Host | smart-8b1bc766-52dd-449b-b924-d7938e75b6a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128054225 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_intg_err.4128054225 |
| Directory | /workspace/10.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.2501590152 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 160484139 ps |
| CPU time | 1.4 seconds |
| Started | Jul 19 04:30:41 PM PDT 24 |
| Finished | Jul 19 04:30:48 PM PDT 24 |
| Peak memory | 204412 kb |
| Host | smart-d50d1618-5b90-435d-ab86-b0ad6d961228 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501590152 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_intg_err.2501590152 |
| Directory | /workspace/9.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.3251638592 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 73448767 ps |
| CPU time | 1.82 seconds |
| Started | Jul 19 04:30:09 PM PDT 24 |
| Finished | Jul 19 04:30:20 PM PDT 24 |
| Peak memory | 204352 kb |
| Host | smart-729d824a-b292-4eee-987f-623b5ef218f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251638592 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_aliasing.3251638592 |
| Directory | /workspace/0.i2c_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.4259775569 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 678095218 ps |
| CPU time | 4.73 seconds |
| Started | Jul 19 04:30:11 PM PDT 24 |
| Finished | Jul 19 04:30:25 PM PDT 24 |
| Peak memory | 204408 kb |
| Host | smart-c694ead0-9784-4943-9c04-745872ef8ef6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259775569 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_bit_bash.4259775569 |
| Directory | /workspace/0.i2c_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.3462022502 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 80444660 ps |
| CPU time | 0.74 seconds |
| Started | Jul 19 04:30:07 PM PDT 24 |
| Finished | Jul 19 04:30:18 PM PDT 24 |
| Peak memory | 204304 kb |
| Host | smart-3ee95653-8336-43f3-9d45-d5bc795b778d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462022502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_hw_reset.3462022502 |
| Directory | /workspace/0.i2c_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.256442005 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 83119338 ps |
| CPU time | 0.84 seconds |
| Started | Jul 19 04:30:11 PM PDT 24 |
| Finished | Jul 19 04:30:21 PM PDT 24 |
| Peak memory | 204372 kb |
| Host | smart-c2cabb7e-77ae-4700-8c4d-c0d08f7eb862 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256442005 -assert nopostproc +UVM_TESTNAME= i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 0.i2c_csr_mem_rw_with_rand_reset.256442005 |
| Directory | /workspace/0.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.i2c_csr_rw.2561676595 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 15818676 ps |
| CPU time | 0.71 seconds |
| Started | Jul 19 04:30:11 PM PDT 24 |
| Finished | Jul 19 04:30:21 PM PDT 24 |
| Peak memory | 204336 kb |
| Host | smart-3c7afb5d-ba61-41d7-b334-acf5a64aabe5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561676595 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_rw.2561676595 |
| Directory | /workspace/0.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.i2c_intr_test.2586343278 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 18199637 ps |
| CPU time | 0.7 seconds |
| Started | Jul 19 04:30:10 PM PDT 24 |
| Finished | Jul 19 04:30:20 PM PDT 24 |
| Peak memory | 204232 kb |
| Host | smart-bce5dbf7-b60b-434c-a556-abea2e8e2c43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586343278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_intr_test.2586343278 |
| Directory | /workspace/0.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.1259972311 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 22731601 ps |
| CPU time | 0.86 seconds |
| Started | Jul 19 04:30:10 PM PDT 24 |
| Finished | Jul 19 04:30:20 PM PDT 24 |
| Peak memory | 204300 kb |
| Host | smart-c8edc682-0bb4-4ea1-826a-b0b1d5cf2b9f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259972311 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_same_csr_ou tstanding.1259972311 |
| Directory | /workspace/0.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/0.i2c_tl_errors.525236622 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 624598099 ps |
| CPU time | 1.55 seconds |
| Started | Jul 19 04:30:12 PM PDT 24 |
| Finished | Jul 19 04:30:22 PM PDT 24 |
| Peak memory | 204500 kb |
| Host | smart-1eb6817a-3c46-4257-b3a2-96e7f70a9e91 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525236622 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_errors.525236622 |
| Directory | /workspace/0.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.729543865 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 46167479 ps |
| CPU time | 1.43 seconds |
| Started | Jul 19 04:30:09 PM PDT 24 |
| Finished | Jul 19 04:30:21 PM PDT 24 |
| Peak memory | 204472 kb |
| Host | smart-0448f2b2-4117-453b-b8dd-67b7d5840c37 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729543865 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_intg_err.729543865 |
| Directory | /workspace/0.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.3581030233 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 170212505 ps |
| CPU time | 1.15 seconds |
| Started | Jul 19 04:30:18 PM PDT 24 |
| Finished | Jul 19 04:30:26 PM PDT 24 |
| Peak memory | 204320 kb |
| Host | smart-21d02886-31d7-4135-a09f-a513407da452 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581030233 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_aliasing.3581030233 |
| Directory | /workspace/1.i2c_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.3549483019 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 909200430 ps |
| CPU time | 2.88 seconds |
| Started | Jul 19 04:30:17 PM PDT 24 |
| Finished | Jul 19 04:30:27 PM PDT 24 |
| Peak memory | 204364 kb |
| Host | smart-4f2f8821-4c47-41cd-b9cc-db66467f5f89 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549483019 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_bit_bash.3549483019 |
| Directory | /workspace/1.i2c_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.897128538 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 40534495 ps |
| CPU time | 0.75 seconds |
| Started | Jul 19 04:30:17 PM PDT 24 |
| Finished | Jul 19 04:30:25 PM PDT 24 |
| Peak memory | 204312 kb |
| Host | smart-c59ddf8f-5160-44b1-8adb-f81f82662c6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897128538 -assert nopostproc +UVM_TESTNAME= i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 1.i2c_csr_mem_rw_with_rand_reset.897128538 |
| Directory | /workspace/1.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.i2c_csr_rw.521065251 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 64890441 ps |
| CPU time | 0.79 seconds |
| Started | Jul 19 04:30:21 PM PDT 24 |
| Finished | Jul 19 04:30:26 PM PDT 24 |
| Peak memory | 204332 kb |
| Host | smart-fd768613-5efc-424b-990c-00a034f1debc |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521065251 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_rw.521065251 |
| Directory | /workspace/1.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.i2c_intr_test.2505879719 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 19646427 ps |
| CPU time | 0.8 seconds |
| Started | Jul 19 04:30:19 PM PDT 24 |
| Finished | Jul 19 04:30:25 PM PDT 24 |
| Peak memory | 204280 kb |
| Host | smart-89d68e44-3799-494c-a098-804f6047f7f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505879719 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_intr_test.2505879719 |
| Directory | /workspace/1.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.1885117022 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 99822744 ps |
| CPU time | 1.05 seconds |
| Started | Jul 19 04:30:18 PM PDT 24 |
| Finished | Jul 19 04:30:26 PM PDT 24 |
| Peak memory | 204380 kb |
| Host | smart-44e96e22-d6e3-4d79-ba2e-cdb204f55559 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885117022 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_same_csr_ou tstanding.1885117022 |
| Directory | /workspace/1.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/1.i2c_tl_errors.3227870939 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 138267070 ps |
| CPU time | 1.52 seconds |
| Started | Jul 19 04:30:09 PM PDT 24 |
| Finished | Jul 19 04:30:20 PM PDT 24 |
| Peak memory | 204476 kb |
| Host | smart-015b9e66-877c-4849-b5f7-4a3e07b4dee3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227870939 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_errors.3227870939 |
| Directory | /workspace/1.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.1360255637 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 109210559 ps |
| CPU time | 0.99 seconds |
| Started | Jul 19 04:30:37 PM PDT 24 |
| Finished | Jul 19 04:30:40 PM PDT 24 |
| Peak memory | 204368 kb |
| Host | smart-5794335a-8ab7-4a4b-a13a-6cb166c7092d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360255637 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 10.i2c_csr_mem_rw_with_rand_reset.1360255637 |
| Directory | /workspace/10.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.i2c_csr_rw.230159184 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 183258173 ps |
| CPU time | 0.75 seconds |
| Started | Jul 19 04:30:38 PM PDT 24 |
| Finished | Jul 19 04:30:42 PM PDT 24 |
| Peak memory | 204308 kb |
| Host | smart-c9315eab-f3f0-416d-9866-ba00b4b2f866 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230159184 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_rw.230159184 |
| Directory | /workspace/10.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.i2c_intr_test.3852217087 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 45311606 ps |
| CPU time | 0.7 seconds |
| Started | Jul 19 04:30:43 PM PDT 24 |
| Finished | Jul 19 04:30:48 PM PDT 24 |
| Peak memory | 204388 kb |
| Host | smart-a8ca07ac-dc4c-4c49-8a58-76ccaa74c2b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852217087 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_intr_test.3852217087 |
| Directory | /workspace/10.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/10.i2c_tl_errors.449674543 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 122515094 ps |
| CPU time | 1.66 seconds |
| Started | Jul 19 04:30:51 PM PDT 24 |
| Finished | Jul 19 04:31:03 PM PDT 24 |
| Peak memory | 204356 kb |
| Host | smart-03e84933-423c-4af4-8154-a3add3abadfb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449674543 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_errors.449674543 |
| Directory | /workspace/10.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.347203608 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 31075344 ps |
| CPU time | 1.34 seconds |
| Started | Jul 19 04:30:39 PM PDT 24 |
| Finished | Jul 19 04:30:45 PM PDT 24 |
| Peak memory | 204460 kb |
| Host | smart-aaee7ede-9985-428b-a926-deb3db6f888c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347203608 -assert nopostproc +UVM_TESTNAME= i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 11.i2c_csr_mem_rw_with_rand_reset.347203608 |
| Directory | /workspace/11.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.i2c_csr_rw.2788483119 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 62802145 ps |
| CPU time | 0.74 seconds |
| Started | Jul 19 04:30:39 PM PDT 24 |
| Finished | Jul 19 04:30:44 PM PDT 24 |
| Peak memory | 204508 kb |
| Host | smart-4aa60376-e566-4c35-8e11-0a7e89cbdd1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788483119 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_rw.2788483119 |
| Directory | /workspace/11.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.i2c_intr_test.4122593689 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 39216027 ps |
| CPU time | 0.69 seconds |
| Started | Jul 19 04:30:37 PM PDT 24 |
| Finished | Jul 19 04:30:40 PM PDT 24 |
| Peak memory | 204252 kb |
| Host | smart-bdbe815d-eba8-43a0-bcc9-6d46be3987ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122593689 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_intr_test.4122593689 |
| Directory | /workspace/11.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.2406413669 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 86804639 ps |
| CPU time | 0.91 seconds |
| Started | Jul 19 04:30:38 PM PDT 24 |
| Finished | Jul 19 04:30:43 PM PDT 24 |
| Peak memory | 204252 kb |
| Host | smart-79157602-e426-473f-9742-c9d69e197d76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406413669 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_same_csr_o utstanding.2406413669 |
| Directory | /workspace/11.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/11.i2c_tl_errors.1714995191 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 234603162 ps |
| CPU time | 2.45 seconds |
| Started | Jul 19 04:30:41 PM PDT 24 |
| Finished | Jul 19 04:30:48 PM PDT 24 |
| Peak memory | 204536 kb |
| Host | smart-07b2403a-0280-468b-b100-f33e27f35f5b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714995191 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_errors.1714995191 |
| Directory | /workspace/11.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.1635156486 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 82153134 ps |
| CPU time | 1.44 seconds |
| Started | Jul 19 04:30:37 PM PDT 24 |
| Finished | Jul 19 04:30:41 PM PDT 24 |
| Peak memory | 204400 kb |
| Host | smart-debf9f0f-f6e3-4db2-bf22-049008e343c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635156486 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_intg_err.1635156486 |
| Directory | /workspace/11.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.3859503252 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 27815690 ps |
| CPU time | 0.87 seconds |
| Started | Jul 19 04:30:37 PM PDT 24 |
| Finished | Jul 19 04:30:39 PM PDT 24 |
| Peak memory | 204416 kb |
| Host | smart-fe9d10dd-82bc-48b6-bba1-9f5fda091c8d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859503252 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 12.i2c_csr_mem_rw_with_rand_reset.3859503252 |
| Directory | /workspace/12.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.i2c_intr_test.2473127564 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 16878163 ps |
| CPU time | 0.65 seconds |
| Started | Jul 19 04:30:39 PM PDT 24 |
| Finished | Jul 19 04:30:43 PM PDT 24 |
| Peak memory | 204584 kb |
| Host | smart-51ad201e-c37f-49f7-ae4f-598f562f0e47 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473127564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_intr_test.2473127564 |
| Directory | /workspace/12.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/12.i2c_tl_errors.4286621754 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 99079064 ps |
| CPU time | 2.29 seconds |
| Started | Jul 19 04:30:38 PM PDT 24 |
| Finished | Jul 19 04:30:44 PM PDT 24 |
| Peak memory | 212584 kb |
| Host | smart-ca4e9189-d93a-4dff-88c7-121c056257fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286621754 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_errors.4286621754 |
| Directory | /workspace/12.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.3267170181 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 287678307 ps |
| CPU time | 1.5 seconds |
| Started | Jul 19 04:30:44 PM PDT 24 |
| Finished | Jul 19 04:30:50 PM PDT 24 |
| Peak memory | 204388 kb |
| Host | smart-6559a5b4-b94b-456e-9d12-2fbf3cb06c74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267170181 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_intg_err.3267170181 |
| Directory | /workspace/12.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.604299314 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 101539783 ps |
| CPU time | 1.35 seconds |
| Started | Jul 19 04:30:38 PM PDT 24 |
| Finished | Jul 19 04:30:42 PM PDT 24 |
| Peak memory | 212644 kb |
| Host | smart-079e9c86-b6c6-436d-855f-bfc7103cc965 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604299314 -assert nopostproc +UVM_TESTNAME= i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 13.i2c_csr_mem_rw_with_rand_reset.604299314 |
| Directory | /workspace/13.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.i2c_csr_rw.564277265 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 107378901 ps |
| CPU time | 0.69 seconds |
| Started | Jul 19 04:30:42 PM PDT 24 |
| Finished | Jul 19 04:30:48 PM PDT 24 |
| Peak memory | 204284 kb |
| Host | smart-4e002c0d-38d6-472b-8bb7-bb9eb61147af |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564277265 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_rw.564277265 |
| Directory | /workspace/13.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.i2c_intr_test.1809562801 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 47277046 ps |
| CPU time | 0.67 seconds |
| Started | Jul 19 04:30:42 PM PDT 24 |
| Finished | Jul 19 04:30:48 PM PDT 24 |
| Peak memory | 204300 kb |
| Host | smart-e75cb639-79d4-4e50-a893-a5d631c3414c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809562801 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_intr_test.1809562801 |
| Directory | /workspace/13.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.954803469 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 73540562 ps |
| CPU time | 1.21 seconds |
| Started | Jul 19 04:30:44 PM PDT 24 |
| Finished | Jul 19 04:30:50 PM PDT 24 |
| Peak memory | 204360 kb |
| Host | smart-72735cb3-befa-444d-8841-1670f7b93775 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954803469 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_same_csr_ou tstanding.954803469 |
| Directory | /workspace/13.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/13.i2c_tl_errors.1460360709 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 79908565 ps |
| CPU time | 1.67 seconds |
| Started | Jul 19 04:30:42 PM PDT 24 |
| Finished | Jul 19 04:30:49 PM PDT 24 |
| Peak memory | 204468 kb |
| Host | smart-9b4f7cf8-a81f-4b25-9bef-a7774ee45829 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460360709 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_errors.1460360709 |
| Directory | /workspace/13.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.3652088359 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 52963850 ps |
| CPU time | 1.36 seconds |
| Started | Jul 19 04:30:46 PM PDT 24 |
| Finished | Jul 19 04:30:51 PM PDT 24 |
| Peak memory | 204448 kb |
| Host | smart-503a22bc-f776-44a0-99be-66b5d8de3a82 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652088359 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_intg_err.3652088359 |
| Directory | /workspace/13.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.1335931367 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 84108889 ps |
| CPU time | 0.88 seconds |
| Started | Jul 19 04:30:41 PM PDT 24 |
| Finished | Jul 19 04:30:47 PM PDT 24 |
| Peak memory | 204396 kb |
| Host | smart-4f06d10b-134f-4833-beb3-287ceec8c620 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335931367 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 14.i2c_csr_mem_rw_with_rand_reset.1335931367 |
| Directory | /workspace/14.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.i2c_csr_rw.4151364999 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 23506031 ps |
| CPU time | 0.71 seconds |
| Started | Jul 19 04:30:39 PM PDT 24 |
| Finished | Jul 19 04:30:44 PM PDT 24 |
| Peak memory | 204292 kb |
| Host | smart-4041ecb7-a382-4b4e-843e-fdf33164244f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151364999 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_rw.4151364999 |
| Directory | /workspace/14.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.i2c_intr_test.1890636588 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 27428335 ps |
| CPU time | 0.65 seconds |
| Started | Jul 19 04:30:42 PM PDT 24 |
| Finished | Jul 19 04:30:48 PM PDT 24 |
| Peak memory | 204260 kb |
| Host | smart-900bed26-e52f-4215-a760-aa0c5dd53def |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890636588 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_intr_test.1890636588 |
| Directory | /workspace/14.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.500062585 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 28795586 ps |
| CPU time | 1.1 seconds |
| Started | Jul 19 04:30:39 PM PDT 24 |
| Finished | Jul 19 04:30:45 PM PDT 24 |
| Peak memory | 204512 kb |
| Host | smart-5065653b-7232-446e-ab02-c51bb64f3bed |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500062585 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_same_csr_ou tstanding.500062585 |
| Directory | /workspace/14.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/14.i2c_tl_errors.1906509204 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 25367754 ps |
| CPU time | 1.1 seconds |
| Started | Jul 19 04:30:37 PM PDT 24 |
| Finished | Jul 19 04:30:40 PM PDT 24 |
| Peak memory | 204560 kb |
| Host | smart-debc1fc3-600e-41dc-b0ba-3d412f6dcfbc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906509204 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_errors.1906509204 |
| Directory | /workspace/14.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.1878934458 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 316906969 ps |
| CPU time | 1.54 seconds |
| Started | Jul 19 04:30:41 PM PDT 24 |
| Finished | Jul 19 04:30:48 PM PDT 24 |
| Peak memory | 204384 kb |
| Host | smart-f4844c92-4d27-41be-8dc7-89f51edfed65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878934458 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_intg_err.1878934458 |
| Directory | /workspace/14.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.1169228485 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 36862027 ps |
| CPU time | 0.96 seconds |
| Started | Jul 19 04:30:40 PM PDT 24 |
| Finished | Jul 19 04:30:46 PM PDT 24 |
| Peak memory | 204364 kb |
| Host | smart-0865b8ca-0453-48fb-bdf9-3911a0b06b1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169228485 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 15.i2c_csr_mem_rw_with_rand_reset.1169228485 |
| Directory | /workspace/15.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.i2c_csr_rw.3055051011 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 22438554 ps |
| CPU time | 0.71 seconds |
| Started | Jul 19 04:30:41 PM PDT 24 |
| Finished | Jul 19 04:30:46 PM PDT 24 |
| Peak memory | 204336 kb |
| Host | smart-0cddd5f4-c07f-458e-91c1-b69fedabc38b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055051011 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_rw.3055051011 |
| Directory | /workspace/15.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.1738580541 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 58133454 ps |
| CPU time | 0.91 seconds |
| Started | Jul 19 04:30:38 PM PDT 24 |
| Finished | Jul 19 04:30:43 PM PDT 24 |
| Peak memory | 204324 kb |
| Host | smart-eaa61729-787a-46e9-967e-20d415b20e49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738580541 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_same_csr_o utstanding.1738580541 |
| Directory | /workspace/15.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/15.i2c_tl_errors.2297148735 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 84516327 ps |
| CPU time | 1.26 seconds |
| Started | Jul 19 04:30:38 PM PDT 24 |
| Finished | Jul 19 04:30:44 PM PDT 24 |
| Peak memory | 204568 kb |
| Host | smart-d3194aaa-92ff-4782-8d93-396a3c230696 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297148735 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_errors.2297148735 |
| Directory | /workspace/15.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.3076794342 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 130539592 ps |
| CPU time | 2.22 seconds |
| Started | Jul 19 04:30:40 PM PDT 24 |
| Finished | Jul 19 04:30:48 PM PDT 24 |
| Peak memory | 204432 kb |
| Host | smart-dcf80c4a-2a19-45e9-8ec0-0e38a6016b23 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076794342 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_intg_err.3076794342 |
| Directory | /workspace/15.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.4028776030 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 41035996 ps |
| CPU time | 0.93 seconds |
| Started | Jul 19 04:30:37 PM PDT 24 |
| Finished | Jul 19 04:30:40 PM PDT 24 |
| Peak memory | 204412 kb |
| Host | smart-33f500eb-1dbf-45e3-8ccc-de831f0807c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028776030 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 16.i2c_csr_mem_rw_with_rand_reset.4028776030 |
| Directory | /workspace/16.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.i2c_csr_rw.3920564573 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 20025934 ps |
| CPU time | 0.78 seconds |
| Started | Jul 19 04:30:41 PM PDT 24 |
| Finished | Jul 19 04:30:47 PM PDT 24 |
| Peak memory | 204336 kb |
| Host | smart-951cae90-0c18-4274-9aec-c78e84d0efaa |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920564573 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_rw.3920564573 |
| Directory | /workspace/16.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.i2c_intr_test.4244650234 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 26798828 ps |
| CPU time | 0.63 seconds |
| Started | Jul 19 04:30:43 PM PDT 24 |
| Finished | Jul 19 04:30:48 PM PDT 24 |
| Peak memory | 204364 kb |
| Host | smart-a3443dd7-3de1-42cb-9dda-2c15e4ad20dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244650234 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_intr_test.4244650234 |
| Directory | /workspace/16.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.4124997032 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 21490548 ps |
| CPU time | 0.88 seconds |
| Started | Jul 19 04:30:42 PM PDT 24 |
| Finished | Jul 19 04:30:48 PM PDT 24 |
| Peak memory | 204380 kb |
| Host | smart-bbd2d7f7-77a1-4ceb-84e6-78948abac65d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124997032 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_same_csr_o utstanding.4124997032 |
| Directory | /workspace/16.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/16.i2c_tl_errors.501779073 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 120767062 ps |
| CPU time | 1.73 seconds |
| Started | Jul 19 04:30:38 PM PDT 24 |
| Finished | Jul 19 04:30:43 PM PDT 24 |
| Peak memory | 204496 kb |
| Host | smart-cbc712ae-7854-4709-bff6-1732cd014c1a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501779073 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_errors.501779073 |
| Directory | /workspace/16.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.3779203925 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 82089999 ps |
| CPU time | 1.44 seconds |
| Started | Jul 19 04:30:39 PM PDT 24 |
| Finished | Jul 19 04:30:45 PM PDT 24 |
| Peak memory | 204404 kb |
| Host | smart-4fece692-de5f-4661-aa36-4255a67f8d57 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779203925 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_intg_err.3779203925 |
| Directory | /workspace/16.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.3568486177 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 151301218 ps |
| CPU time | 1.53 seconds |
| Started | Jul 19 04:30:40 PM PDT 24 |
| Finished | Jul 19 04:30:47 PM PDT 24 |
| Peak memory | 212728 kb |
| Host | smart-b9ad16ee-6fa9-4b2e-8d99-d2d1d63fec4f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568486177 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 17.i2c_csr_mem_rw_with_rand_reset.3568486177 |
| Directory | /workspace/17.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.i2c_csr_rw.2285173829 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 22359162 ps |
| CPU time | 0.67 seconds |
| Started | Jul 19 04:30:37 PM PDT 24 |
| Finished | Jul 19 04:30:40 PM PDT 24 |
| Peak memory | 204308 kb |
| Host | smart-7f1baaff-e9cf-4e3f-9443-236187cdd509 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285173829 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_rw.2285173829 |
| Directory | /workspace/17.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.i2c_intr_test.4115309727 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 40896809 ps |
| CPU time | 0.67 seconds |
| Started | Jul 19 04:30:39 PM PDT 24 |
| Finished | Jul 19 04:30:44 PM PDT 24 |
| Peak memory | 204280 kb |
| Host | smart-77410986-44d9-49ce-89d0-d78277fb9d1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115309727 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_intr_test.4115309727 |
| Directory | /workspace/17.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/17.i2c_tl_errors.2362274390 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 141184045 ps |
| CPU time | 2.55 seconds |
| Started | Jul 19 04:30:40 PM PDT 24 |
| Finished | Jul 19 04:30:48 PM PDT 24 |
| Peak memory | 204548 kb |
| Host | smart-67df18e2-1ee4-400e-95c6-c6daca6d0b50 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362274390 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_errors.2362274390 |
| Directory | /workspace/17.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.3113061723 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 145275740 ps |
| CPU time | 2.32 seconds |
| Started | Jul 19 04:30:43 PM PDT 24 |
| Finished | Jul 19 04:30:50 PM PDT 24 |
| Peak memory | 204344 kb |
| Host | smart-6ccb4f0f-4425-444f-83bd-e301c546dde8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113061723 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_intg_err.3113061723 |
| Directory | /workspace/17.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.2967520938 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 180981313 ps |
| CPU time | 1 seconds |
| Started | Jul 19 04:30:48 PM PDT 24 |
| Finished | Jul 19 04:30:52 PM PDT 24 |
| Peak memory | 204412 kb |
| Host | smart-bb40ae8b-9f95-4e10-99bb-c99b55e1f05b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967520938 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 18.i2c_csr_mem_rw_with_rand_reset.2967520938 |
| Directory | /workspace/18.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.i2c_csr_rw.1259750088 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 90712585 ps |
| CPU time | 0.74 seconds |
| Started | Jul 19 04:30:50 PM PDT 24 |
| Finished | Jul 19 04:31:01 PM PDT 24 |
| Peak memory | 204292 kb |
| Host | smart-3a2e3145-02a5-444a-a9b7-4ef54ed5499f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259750088 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_rw.1259750088 |
| Directory | /workspace/18.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.i2c_intr_test.931130069 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 15982933 ps |
| CPU time | 0.69 seconds |
| Started | Jul 19 04:30:50 PM PDT 24 |
| Finished | Jul 19 04:31:01 PM PDT 24 |
| Peak memory | 204580 kb |
| Host | smart-293d53da-5bb6-4509-8251-0c9b9fd2f98a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931130069 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_intr_test.931130069 |
| Directory | /workspace/18.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.1655872252 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 69339935 ps |
| CPU time | 1.24 seconds |
| Started | Jul 19 04:30:54 PM PDT 24 |
| Finished | Jul 19 04:31:11 PM PDT 24 |
| Peak memory | 204388 kb |
| Host | smart-9a6d5939-8ba4-4cd6-8452-3f7518058cef |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655872252 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_same_csr_o utstanding.1655872252 |
| Directory | /workspace/18.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/18.i2c_tl_errors.455626987 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 121944000 ps |
| CPU time | 1.55 seconds |
| Started | Jul 19 04:30:40 PM PDT 24 |
| Finished | Jul 19 04:30:47 PM PDT 24 |
| Peak memory | 204512 kb |
| Host | smart-96eb8ccb-561f-4832-8cea-bc9f4972ba7a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455626987 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_errors.455626987 |
| Directory | /workspace/18.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.2254713210 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 141394949 ps |
| CPU time | 0.97 seconds |
| Started | Jul 19 04:30:54 PM PDT 24 |
| Finished | Jul 19 04:31:11 PM PDT 24 |
| Peak memory | 204336 kb |
| Host | smart-7f1c232c-0d8d-41a9-8806-9631ec3aaa17 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254713210 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 19.i2c_csr_mem_rw_with_rand_reset.2254713210 |
| Directory | /workspace/19.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.i2c_csr_rw.807039165 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 88525712 ps |
| CPU time | 0.87 seconds |
| Started | Jul 19 04:30:53 PM PDT 24 |
| Finished | Jul 19 04:31:08 PM PDT 24 |
| Peak memory | 204312 kb |
| Host | smart-bddea22d-c4e6-45c9-892e-01fae670497e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807039165 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_rw.807039165 |
| Directory | /workspace/19.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.i2c_intr_test.1726502021 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 18412613 ps |
| CPU time | 0.66 seconds |
| Started | Jul 19 04:30:50 PM PDT 24 |
| Finished | Jul 19 04:30:58 PM PDT 24 |
| Peak memory | 204312 kb |
| Host | smart-50b5af5c-6397-4bb2-8dc3-292a1520b0d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726502021 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_intr_test.1726502021 |
| Directory | /workspace/19.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.3428901767 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 33215127 ps |
| CPU time | 0.86 seconds |
| Started | Jul 19 04:30:54 PM PDT 24 |
| Finished | Jul 19 04:31:10 PM PDT 24 |
| Peak memory | 204264 kb |
| Host | smart-d71e7695-16ed-48cd-955f-0863139e3c2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428901767 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_same_csr_o utstanding.3428901767 |
| Directory | /workspace/19.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/19.i2c_tl_errors.2911910888 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 50408352 ps |
| CPU time | 1.19 seconds |
| Started | Jul 19 04:30:54 PM PDT 24 |
| Finished | Jul 19 04:31:10 PM PDT 24 |
| Peak memory | 204496 kb |
| Host | smart-ecaa1489-37ca-4ed2-8509-5f9081b75065 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911910888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_errors.2911910888 |
| Directory | /workspace/19.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.849370500 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 88597334 ps |
| CPU time | 1.19 seconds |
| Started | Jul 19 04:30:18 PM PDT 24 |
| Finished | Jul 19 04:30:25 PM PDT 24 |
| Peak memory | 204428 kb |
| Host | smart-a0be44b8-7065-49ae-80aa-ec3a5ea7532d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849370500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_aliasing.849370500 |
| Directory | /workspace/2.i2c_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.2844053578 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 1089459695 ps |
| CPU time | 2.59 seconds |
| Started | Jul 19 04:30:20 PM PDT 24 |
| Finished | Jul 19 04:30:28 PM PDT 24 |
| Peak memory | 204700 kb |
| Host | smart-7508df4e-2fc4-4c8e-be03-9b9dacb40d4c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844053578 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_bit_bash.2844053578 |
| Directory | /workspace/2.i2c_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.1728610859 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 34697721 ps |
| CPU time | 0.68 seconds |
| Started | Jul 19 04:30:21 PM PDT 24 |
| Finished | Jul 19 04:30:26 PM PDT 24 |
| Peak memory | 204252 kb |
| Host | smart-8eae11a3-3afd-49a2-9cbf-bffc491f4bc2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728610859 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_hw_reset.1728610859 |
| Directory | /workspace/2.i2c_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.1257408639 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 25463431 ps |
| CPU time | 0.77 seconds |
| Started | Jul 19 04:30:20 PM PDT 24 |
| Finished | Jul 19 04:30:26 PM PDT 24 |
| Peak memory | 204392 kb |
| Host | smart-815df0ab-6e50-4ce6-ba8b-4ad6259a5ab1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257408639 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 2.i2c_csr_mem_rw_with_rand_reset.1257408639 |
| Directory | /workspace/2.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.i2c_csr_rw.3202668760 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 61777907 ps |
| CPU time | 0.71 seconds |
| Started | Jul 19 04:30:19 PM PDT 24 |
| Finished | Jul 19 04:30:25 PM PDT 24 |
| Peak memory | 204296 kb |
| Host | smart-8656f38b-7cb6-45a5-b20d-549d96386e5a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202668760 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_rw.3202668760 |
| Directory | /workspace/2.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.i2c_intr_test.1578856983 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 35518804 ps |
| CPU time | 0.68 seconds |
| Started | Jul 19 04:30:21 PM PDT 24 |
| Finished | Jul 19 04:30:26 PM PDT 24 |
| Peak memory | 204296 kb |
| Host | smart-8182c7ea-0ddc-4764-836b-fa776c474b55 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578856983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_intr_test.1578856983 |
| Directory | /workspace/2.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.4222407613 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 211105432 ps |
| CPU time | 1.06 seconds |
| Started | Jul 19 04:30:17 PM PDT 24 |
| Finished | Jul 19 04:30:25 PM PDT 24 |
| Peak memory | 204460 kb |
| Host | smart-73e287db-d1f0-4f46-98a6-e50400f6adce |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222407613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_same_csr_ou tstanding.4222407613 |
| Directory | /workspace/2.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/2.i2c_tl_errors.2320851260 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 192246389 ps |
| CPU time | 2.25 seconds |
| Started | Jul 19 04:30:17 PM PDT 24 |
| Finished | Jul 19 04:30:26 PM PDT 24 |
| Peak memory | 204464 kb |
| Host | smart-d70dc18d-6ee8-4d4a-b531-148a28075e07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320851260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_errors.2320851260 |
| Directory | /workspace/2.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.2540410013 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 84328094 ps |
| CPU time | 2.1 seconds |
| Started | Jul 19 04:30:19 PM PDT 24 |
| Finished | Jul 19 04:30:27 PM PDT 24 |
| Peak memory | 204468 kb |
| Host | smart-c7241ae1-bd9a-4f1c-9655-1ae5be68e06f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540410013 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_intg_err.2540410013 |
| Directory | /workspace/2.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/21.i2c_intr_test.3175073125 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 16460762 ps |
| CPU time | 0.67 seconds |
| Started | Jul 19 04:30:50 PM PDT 24 |
| Finished | Jul 19 04:30:57 PM PDT 24 |
| Peak memory | 204308 kb |
| Host | smart-ca3d77a6-82fa-40f4-9e2f-55431b1baf63 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175073125 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.i2c_intr_test.3175073125 |
| Directory | /workspace/21.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/22.i2c_intr_test.377536181 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 26544470 ps |
| CPU time | 0.68 seconds |
| Started | Jul 19 04:30:59 PM PDT 24 |
| Finished | Jul 19 04:31:16 PM PDT 24 |
| Peak memory | 204280 kb |
| Host | smart-be5c09da-b22d-46c6-b03d-246ef9a8ec3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377536181 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.i2c_intr_test.377536181 |
| Directory | /workspace/22.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/23.i2c_intr_test.1697829739 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 21589282 ps |
| CPU time | 0.67 seconds |
| Started | Jul 19 04:30:56 PM PDT 24 |
| Finished | Jul 19 04:31:13 PM PDT 24 |
| Peak memory | 204296 kb |
| Host | smart-22fad448-4e3f-44bc-a481-b19e8e00be5a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697829739 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.i2c_intr_test.1697829739 |
| Directory | /workspace/23.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/24.i2c_intr_test.1840808038 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 40839613 ps |
| CPU time | 0.65 seconds |
| Started | Jul 19 04:30:55 PM PDT 24 |
| Finished | Jul 19 04:31:12 PM PDT 24 |
| Peak memory | 204308 kb |
| Host | smart-aa8682a2-fe5d-458d-b4ef-0ef6653f33fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840808038 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.i2c_intr_test.1840808038 |
| Directory | /workspace/24.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/25.i2c_intr_test.328982884 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 61353087 ps |
| CPU time | 0.63 seconds |
| Started | Jul 19 04:30:51 PM PDT 24 |
| Finished | Jul 19 04:31:04 PM PDT 24 |
| Peak memory | 204300 kb |
| Host | smart-a7023276-dacf-4380-a142-0949ab018c9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328982884 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.i2c_intr_test.328982884 |
| Directory | /workspace/25.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/26.i2c_intr_test.2582587931 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 32262464 ps |
| CPU time | 0.66 seconds |
| Started | Jul 19 04:30:52 PM PDT 24 |
| Finished | Jul 19 04:31:07 PM PDT 24 |
| Peak memory | 204388 kb |
| Host | smart-81c944f0-ace6-452d-9174-087da3750ef6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582587931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.i2c_intr_test.2582587931 |
| Directory | /workspace/26.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/28.i2c_intr_test.1310968424 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 47489280 ps |
| CPU time | 0.65 seconds |
| Started | Jul 19 04:30:50 PM PDT 24 |
| Finished | Jul 19 04:31:01 PM PDT 24 |
| Peak memory | 204316 kb |
| Host | smart-c6fde701-40a7-493a-9896-697e68838d24 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310968424 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.i2c_intr_test.1310968424 |
| Directory | /workspace/28.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/29.i2c_intr_test.3755936785 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 34286159 ps |
| CPU time | 0.64 seconds |
| Started | Jul 19 04:30:50 PM PDT 24 |
| Finished | Jul 19 04:30:58 PM PDT 24 |
| Peak memory | 204308 kb |
| Host | smart-4e9c512f-dc8f-476f-b9c9-f71c53a539ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755936785 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.i2c_intr_test.3755936785 |
| Directory | /workspace/29.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.1069061941 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 428635510 ps |
| CPU time | 1.9 seconds |
| Started | Jul 19 04:30:27 PM PDT 24 |
| Finished | Jul 19 04:30:32 PM PDT 24 |
| Peak memory | 204408 kb |
| Host | smart-ee354f36-45bc-49d5-8750-aa3f32a7039c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069061941 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_aliasing.1069061941 |
| Directory | /workspace/3.i2c_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.1921572398 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 191869394 ps |
| CPU time | 2.66 seconds |
| Started | Jul 19 04:30:27 PM PDT 24 |
| Finished | Jul 19 04:30:32 PM PDT 24 |
| Peak memory | 204424 kb |
| Host | smart-5b253fca-441f-4ac0-8a61-fe8fb7d95fc2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921572398 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_bit_bash.1921572398 |
| Directory | /workspace/3.i2c_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.i2c_csr_rw.1040497970 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 33570620 ps |
| CPU time | 0.72 seconds |
| Started | Jul 19 04:30:26 PM PDT 24 |
| Finished | Jul 19 04:30:30 PM PDT 24 |
| Peak memory | 204280 kb |
| Host | smart-d7848da1-b759-4ce9-be9b-63c52bbc602a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040497970 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_rw.1040497970 |
| Directory | /workspace/3.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.i2c_intr_test.3713817938 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 47088612 ps |
| CPU time | 0.64 seconds |
| Started | Jul 19 04:30:26 PM PDT 24 |
| Finished | Jul 19 04:30:30 PM PDT 24 |
| Peak memory | 204360 kb |
| Host | smart-e0db6b5d-c837-4152-b059-4cbcdf37aaef |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713817938 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_intr_test.3713817938 |
| Directory | /workspace/3.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.3663266943 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 49632361 ps |
| CPU time | 0.76 seconds |
| Started | Jul 19 04:30:28 PM PDT 24 |
| Finished | Jul 19 04:30:31 PM PDT 24 |
| Peak memory | 204256 kb |
| Host | smart-89dc1bd3-a5a7-4194-8090-ecb6426fb556 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663266943 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_same_csr_ou tstanding.3663266943 |
| Directory | /workspace/3.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/3.i2c_tl_errors.2887028674 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 46991600 ps |
| CPU time | 2.42 seconds |
| Started | Jul 19 04:30:20 PM PDT 24 |
| Finished | Jul 19 04:30:27 PM PDT 24 |
| Peak memory | 204796 kb |
| Host | smart-dd2a1b15-91f7-441f-93e6-0ed11dce2c7a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887028674 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_errors.2887028674 |
| Directory | /workspace/3.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.3821852649 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 283097269 ps |
| CPU time | 1.39 seconds |
| Started | Jul 19 04:30:28 PM PDT 24 |
| Finished | Jul 19 04:30:32 PM PDT 24 |
| Peak memory | 204376 kb |
| Host | smart-cb9384c1-a82b-4883-b7ce-f36ac311d697 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821852649 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_intg_err.3821852649 |
| Directory | /workspace/3.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/30.i2c_intr_test.1331953813 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 17923401 ps |
| CPU time | 0.72 seconds |
| Started | Jul 19 04:30:53 PM PDT 24 |
| Finished | Jul 19 04:31:08 PM PDT 24 |
| Peak memory | 204388 kb |
| Host | smart-7ad9575e-3c29-4065-a2a3-f1c39860c792 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331953813 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.i2c_intr_test.1331953813 |
| Directory | /workspace/30.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/31.i2c_intr_test.3450467521 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 18519247 ps |
| CPU time | 0.64 seconds |
| Started | Jul 19 04:30:51 PM PDT 24 |
| Finished | Jul 19 04:31:03 PM PDT 24 |
| Peak memory | 204304 kb |
| Host | smart-afb5ab4b-59df-4845-8de5-4a306acbca95 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450467521 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.i2c_intr_test.3450467521 |
| Directory | /workspace/31.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/32.i2c_intr_test.721463897 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 17908200 ps |
| CPU time | 0.64 seconds |
| Started | Jul 19 04:30:50 PM PDT 24 |
| Finished | Jul 19 04:31:01 PM PDT 24 |
| Peak memory | 204312 kb |
| Host | smart-ba3c2751-1a2c-4a9e-8148-ad892d259798 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721463897 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.i2c_intr_test.721463897 |
| Directory | /workspace/32.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/33.i2c_intr_test.626422394 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 19392514 ps |
| CPU time | 0.67 seconds |
| Started | Jul 19 04:30:52 PM PDT 24 |
| Finished | Jul 19 04:31:06 PM PDT 24 |
| Peak memory | 204248 kb |
| Host | smart-58dba1aa-a879-4f3f-a98f-afdce4b1c7c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626422394 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.i2c_intr_test.626422394 |
| Directory | /workspace/33.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/34.i2c_intr_test.4214437604 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 26542868 ps |
| CPU time | 0.65 seconds |
| Started | Jul 19 04:30:52 PM PDT 24 |
| Finished | Jul 19 04:31:06 PM PDT 24 |
| Peak memory | 204308 kb |
| Host | smart-42bce750-f919-4254-ae23-f894494eee8f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214437604 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.i2c_intr_test.4214437604 |
| Directory | /workspace/34.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/35.i2c_intr_test.1266946590 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 33380804 ps |
| CPU time | 0.67 seconds |
| Started | Jul 19 04:30:50 PM PDT 24 |
| Finished | Jul 19 04:30:56 PM PDT 24 |
| Peak memory | 204364 kb |
| Host | smart-73594caf-9896-4ef4-b422-94cf11afb8c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266946590 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.i2c_intr_test.1266946590 |
| Directory | /workspace/35.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/36.i2c_intr_test.1670783137 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 20301979 ps |
| CPU time | 0.68 seconds |
| Started | Jul 19 04:30:47 PM PDT 24 |
| Finished | Jul 19 04:30:50 PM PDT 24 |
| Peak memory | 204312 kb |
| Host | smart-2fe1db31-8d34-40c7-9691-c0a626880d14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670783137 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.i2c_intr_test.1670783137 |
| Directory | /workspace/36.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/37.i2c_intr_test.159019811 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 60095579 ps |
| CPU time | 0.69 seconds |
| Started | Jul 19 04:30:53 PM PDT 24 |
| Finished | Jul 19 04:31:09 PM PDT 24 |
| Peak memory | 204388 kb |
| Host | smart-207999fd-b775-4e41-9a36-02fb6b39108d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159019811 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.i2c_intr_test.159019811 |
| Directory | /workspace/37.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/38.i2c_intr_test.1815555281 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 19646068 ps |
| CPU time | 0.72 seconds |
| Started | Jul 19 04:30:52 PM PDT 24 |
| Finished | Jul 19 04:31:05 PM PDT 24 |
| Peak memory | 204248 kb |
| Host | smart-5a3f92b9-f77f-4669-a719-9e119ee3b751 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815555281 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.i2c_intr_test.1815555281 |
| Directory | /workspace/38.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/39.i2c_intr_test.620796627 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 32815572 ps |
| CPU time | 0.73 seconds |
| Started | Jul 19 04:30:53 PM PDT 24 |
| Finished | Jul 19 04:31:08 PM PDT 24 |
| Peak memory | 204288 kb |
| Host | smart-8efd5811-e6bc-40b8-95b5-b6712133528c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620796627 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.i2c_intr_test.620796627 |
| Directory | /workspace/39.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.1011729106 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 441976645 ps |
| CPU time | 1.94 seconds |
| Started | Jul 19 04:30:28 PM PDT 24 |
| Finished | Jul 19 04:30:33 PM PDT 24 |
| Peak memory | 204412 kb |
| Host | smart-aacf59db-64b4-4359-bf90-37023886642f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011729106 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_aliasing.1011729106 |
| Directory | /workspace/4.i2c_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.1165319296 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 369799747 ps |
| CPU time | 2.74 seconds |
| Started | Jul 19 04:30:26 PM PDT 24 |
| Finished | Jul 19 04:30:32 PM PDT 24 |
| Peak memory | 204356 kb |
| Host | smart-47982808-5363-4d33-8356-5122922c5ad0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165319296 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_bit_bash.1165319296 |
| Directory | /workspace/4.i2c_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.3492988243 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 19334574 ps |
| CPU time | 0.73 seconds |
| Started | Jul 19 04:30:27 PM PDT 24 |
| Finished | Jul 19 04:30:31 PM PDT 24 |
| Peak memory | 204336 kb |
| Host | smart-c0460a0e-9ce0-4a2c-be9a-7f3032e794de |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492988243 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_hw_reset.3492988243 |
| Directory | /workspace/4.i2c_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.1636590372 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 36803450 ps |
| CPU time | 0.98 seconds |
| Started | Jul 19 04:30:24 PM PDT 24 |
| Finished | Jul 19 04:30:29 PM PDT 24 |
| Peak memory | 204492 kb |
| Host | smart-36028050-aa3e-458c-bfc2-67629bdf463e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636590372 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 4.i2c_csr_mem_rw_with_rand_reset.1636590372 |
| Directory | /workspace/4.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.i2c_csr_rw.342510811 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 19389533 ps |
| CPU time | 0.69 seconds |
| Started | Jul 19 04:30:26 PM PDT 24 |
| Finished | Jul 19 04:30:30 PM PDT 24 |
| Peak memory | 204284 kb |
| Host | smart-8f956482-ab80-4268-aca4-3f2beab6ed8b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342510811 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_rw.342510811 |
| Directory | /workspace/4.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.3253395035 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 176700975 ps |
| CPU time | 1.09 seconds |
| Started | Jul 19 04:30:28 PM PDT 24 |
| Finished | Jul 19 04:30:32 PM PDT 24 |
| Peak memory | 204416 kb |
| Host | smart-0fa0cc2f-62cb-4937-9e6b-6789192e1b1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253395035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_same_csr_ou tstanding.3253395035 |
| Directory | /workspace/4.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.775791716 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 104000079 ps |
| CPU time | 2.09 seconds |
| Started | Jul 19 04:30:28 PM PDT 24 |
| Finished | Jul 19 04:30:33 PM PDT 24 |
| Peak memory | 204472 kb |
| Host | smart-a7531690-e032-4695-99af-63dab62c7923 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775791716 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_intg_err.775791716 |
| Directory | /workspace/4.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/40.i2c_intr_test.1779353837 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 43094410 ps |
| CPU time | 0.71 seconds |
| Started | Jul 19 04:30:51 PM PDT 24 |
| Finished | Jul 19 04:31:02 PM PDT 24 |
| Peak memory | 204312 kb |
| Host | smart-a4ff6cd0-a4f3-4718-b36a-2a6373ff7a7a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779353837 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.i2c_intr_test.1779353837 |
| Directory | /workspace/40.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/41.i2c_intr_test.1120812918 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 30311679 ps |
| CPU time | 0.68 seconds |
| Started | Jul 19 04:30:54 PM PDT 24 |
| Finished | Jul 19 04:31:09 PM PDT 24 |
| Peak memory | 204608 kb |
| Host | smart-b544937a-78d3-4754-a566-dade374c49f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120812918 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.i2c_intr_test.1120812918 |
| Directory | /workspace/41.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/42.i2c_intr_test.1802855784 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 24350909 ps |
| CPU time | 0.64 seconds |
| Started | Jul 19 04:30:50 PM PDT 24 |
| Finished | Jul 19 04:30:57 PM PDT 24 |
| Peak memory | 204308 kb |
| Host | smart-b3b72ab7-165c-4d25-b395-09f32434e680 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802855784 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.i2c_intr_test.1802855784 |
| Directory | /workspace/42.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/43.i2c_intr_test.2274529711 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 16574290 ps |
| CPU time | 0.71 seconds |
| Started | Jul 19 04:30:53 PM PDT 24 |
| Finished | Jul 19 04:31:08 PM PDT 24 |
| Peak memory | 204312 kb |
| Host | smart-caa216d4-d8c8-4fd9-8a93-7fe1cd1f3a71 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274529711 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.i2c_intr_test.2274529711 |
| Directory | /workspace/43.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/44.i2c_intr_test.2995971271 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 18830995 ps |
| CPU time | 0.69 seconds |
| Started | Jul 19 04:30:52 PM PDT 24 |
| Finished | Jul 19 04:31:06 PM PDT 24 |
| Peak memory | 204312 kb |
| Host | smart-226cb773-a195-473d-bde0-f0da9023245d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995971271 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.i2c_intr_test.2995971271 |
| Directory | /workspace/44.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/45.i2c_intr_test.937803084 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 28276715 ps |
| CPU time | 0.64 seconds |
| Started | Jul 19 04:30:55 PM PDT 24 |
| Finished | Jul 19 04:31:11 PM PDT 24 |
| Peak memory | 204296 kb |
| Host | smart-5129ba4c-c6a8-4468-8071-fc7bdc147494 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937803084 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.i2c_intr_test.937803084 |
| Directory | /workspace/45.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/46.i2c_intr_test.4259893656 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 33866552 ps |
| CPU time | 0.67 seconds |
| Started | Jul 19 04:30:49 PM PDT 24 |
| Finished | Jul 19 04:30:53 PM PDT 24 |
| Peak memory | 204304 kb |
| Host | smart-04764ba8-d17b-4353-9473-dc8f2c939277 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259893656 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.i2c_intr_test.4259893656 |
| Directory | /workspace/46.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/47.i2c_intr_test.101879770 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 18522382 ps |
| CPU time | 0.66 seconds |
| Started | Jul 19 04:30:53 PM PDT 24 |
| Finished | Jul 19 04:31:08 PM PDT 24 |
| Peak memory | 204236 kb |
| Host | smart-5573e755-e9e0-4230-8828-21738842877d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101879770 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.i2c_intr_test.101879770 |
| Directory | /workspace/47.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/48.i2c_intr_test.3699349600 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 31435550 ps |
| CPU time | 0.64 seconds |
| Started | Jul 19 04:30:49 PM PDT 24 |
| Finished | Jul 19 04:30:54 PM PDT 24 |
| Peak memory | 204312 kb |
| Host | smart-7474d53c-7da0-4d3b-985a-a0d2538e286e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699349600 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.i2c_intr_test.3699349600 |
| Directory | /workspace/48.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/49.i2c_intr_test.1433153919 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 177236800 ps |
| CPU time | 0.65 seconds |
| Started | Jul 19 04:30:54 PM PDT 24 |
| Finished | Jul 19 04:31:10 PM PDT 24 |
| Peak memory | 204156 kb |
| Host | smart-8c785501-c5a1-4583-8fb7-7c8f6db9d57d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433153919 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.i2c_intr_test.1433153919 |
| Directory | /workspace/49.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.2246826941 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 23817645 ps |
| CPU time | 1.1 seconds |
| Started | Jul 19 04:30:32 PM PDT 24 |
| Finished | Jul 19 04:30:35 PM PDT 24 |
| Peak memory | 204360 kb |
| Host | smart-172b1dd5-3cae-4588-9c38-9273f813b8a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246826941 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 5.i2c_csr_mem_rw_with_rand_reset.2246826941 |
| Directory | /workspace/5.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.i2c_csr_rw.528518651 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 50204533 ps |
| CPU time | 0.71 seconds |
| Started | Jul 19 04:30:32 PM PDT 24 |
| Finished | Jul 19 04:30:35 PM PDT 24 |
| Peak memory | 204336 kb |
| Host | smart-98f20af6-6987-43ca-b365-5ed6c55a41fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528518651 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_rw.528518651 |
| Directory | /workspace/5.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.i2c_intr_test.1872551195 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 22760716 ps |
| CPU time | 0.61 seconds |
| Started | Jul 19 04:30:27 PM PDT 24 |
| Finished | Jul 19 04:30:31 PM PDT 24 |
| Peak memory | 204224 kb |
| Host | smart-4fd6be1e-d056-43e3-9971-09484c560eab |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872551195 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_intr_test.1872551195 |
| Directory | /workspace/5.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.2654537870 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 163917492 ps |
| CPU time | 0.82 seconds |
| Started | Jul 19 04:30:30 PM PDT 24 |
| Finished | Jul 19 04:30:33 PM PDT 24 |
| Peak memory | 204308 kb |
| Host | smart-f56d2fa6-d39a-48a0-865d-53b7babac3e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654537870 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_same_csr_ou tstanding.2654537870 |
| Directory | /workspace/5.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.i2c_tl_errors.406203123 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 101525895 ps |
| CPU time | 2.35 seconds |
| Started | Jul 19 04:30:32 PM PDT 24 |
| Finished | Jul 19 04:30:36 PM PDT 24 |
| Peak memory | 204484 kb |
| Host | smart-90d23feb-f52c-4b06-8512-61093822b1b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406203123 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_errors.406203123 |
| Directory | /workspace/5.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.680846208 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 53999924 ps |
| CPU time | 1.44 seconds |
| Started | Jul 19 04:30:26 PM PDT 24 |
| Finished | Jul 19 04:30:31 PM PDT 24 |
| Peak memory | 204412 kb |
| Host | smart-ca39ab35-4957-4abd-b769-a7c3e50f1027 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680846208 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_intg_err.680846208 |
| Directory | /workspace/5.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.12550967 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 27695985 ps |
| CPU time | 1.25 seconds |
| Started | Jul 19 04:30:27 PM PDT 24 |
| Finished | Jul 19 04:30:31 PM PDT 24 |
| Peak memory | 212676 kb |
| Host | smart-e966828d-aa64-4509-ae13-cdc341b65240 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12550967 -assert nopostproc +UVM_TESTNAME=i 2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 6.i2c_csr_mem_rw_with_rand_reset.12550967 |
| Directory | /workspace/6.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.i2c_csr_rw.3255354860 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 55940856 ps |
| CPU time | 0.7 seconds |
| Started | Jul 19 04:30:25 PM PDT 24 |
| Finished | Jul 19 04:30:29 PM PDT 24 |
| Peak memory | 204268 kb |
| Host | smart-cd9707ea-abd5-4766-a998-aeab7eca0d1a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255354860 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_rw.3255354860 |
| Directory | /workspace/6.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.i2c_tl_errors.4090027035 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 48983604 ps |
| CPU time | 1.16 seconds |
| Started | Jul 19 04:30:26 PM PDT 24 |
| Finished | Jul 19 04:30:31 PM PDT 24 |
| Peak memory | 204468 kb |
| Host | smart-e287f5f2-2c3a-4aa4-89f9-635f25e0389b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090027035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_errors.4090027035 |
| Directory | /workspace/6.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.4169409330 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 36256665 ps |
| CPU time | 0.77 seconds |
| Started | Jul 19 04:30:50 PM PDT 24 |
| Finished | Jul 19 04:31:00 PM PDT 24 |
| Peak memory | 204228 kb |
| Host | smart-f1ce8711-b998-4807-be04-65db66583bba |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169409330 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 7.i2c_csr_mem_rw_with_rand_reset.4169409330 |
| Directory | /workspace/7.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.i2c_csr_rw.1151266172 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 20719265 ps |
| CPU time | 0.71 seconds |
| Started | Jul 19 04:30:27 PM PDT 24 |
| Finished | Jul 19 04:30:31 PM PDT 24 |
| Peak memory | 204228 kb |
| Host | smart-0845a38e-f924-448c-9b6e-7977c0b6d4eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151266172 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_rw.1151266172 |
| Directory | /workspace/7.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.i2c_intr_test.62485910 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 38663012 ps |
| CPU time | 0.7 seconds |
| Started | Jul 19 04:30:28 PM PDT 24 |
| Finished | Jul 19 04:30:31 PM PDT 24 |
| Peak memory | 204212 kb |
| Host | smart-e0ec5566-e085-43d1-88ca-90f3f4381128 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62485910 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_intr_test.62485910 |
| Directory | /workspace/7.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.1123298573 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 80768946 ps |
| CPU time | 1.07 seconds |
| Started | Jul 19 04:30:26 PM PDT 24 |
| Finished | Jul 19 04:30:31 PM PDT 24 |
| Peak memory | 204440 kb |
| Host | smart-2cf2785e-3813-432c-867a-7e54078c8e96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123298573 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_same_csr_ou tstanding.1123298573 |
| Directory | /workspace/7.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.i2c_tl_errors.1033906058 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 379317164 ps |
| CPU time | 1.42 seconds |
| Started | Jul 19 04:30:26 PM PDT 24 |
| Finished | Jul 19 04:30:31 PM PDT 24 |
| Peak memory | 204592 kb |
| Host | smart-38c7f861-19ab-4f70-947d-e1f7c074653a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033906058 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_errors.1033906058 |
| Directory | /workspace/7.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.720946901 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 87625011 ps |
| CPU time | 1.42 seconds |
| Started | Jul 19 04:30:29 PM PDT 24 |
| Finished | Jul 19 04:30:33 PM PDT 24 |
| Peak memory | 204400 kb |
| Host | smart-968b14dc-11bf-4e21-8c78-9973fb1fc780 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720946901 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_intg_err.720946901 |
| Directory | /workspace/7.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.1754465478 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 30236685 ps |
| CPU time | 1.25 seconds |
| Started | Jul 19 04:30:36 PM PDT 24 |
| Finished | Jul 19 04:30:39 PM PDT 24 |
| Peak memory | 213844 kb |
| Host | smart-71cf0e0d-8e7f-42b7-a347-aec6cc8a001d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754465478 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 8.i2c_csr_mem_rw_with_rand_reset.1754465478 |
| Directory | /workspace/8.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.i2c_csr_rw.3054241116 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 28334839 ps |
| CPU time | 0.68 seconds |
| Started | Jul 19 04:30:40 PM PDT 24 |
| Finished | Jul 19 04:30:46 PM PDT 24 |
| Peak memory | 204280 kb |
| Host | smart-aa87f88a-aa5d-4429-ada6-1f58edc93bb4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054241116 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_rw.3054241116 |
| Directory | /workspace/8.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.i2c_intr_test.2226486158 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 53722112 ps |
| CPU time | 0.61 seconds |
| Started | Jul 19 04:30:35 PM PDT 24 |
| Finished | Jul 19 04:30:36 PM PDT 24 |
| Peak memory | 204268 kb |
| Host | smart-3b53641b-5c88-48cf-95c6-d9fbeebff4bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226486158 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_intr_test.2226486158 |
| Directory | /workspace/8.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.1125205558 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 78242966 ps |
| CPU time | 1.14 seconds |
| Started | Jul 19 04:30:39 PM PDT 24 |
| Finished | Jul 19 04:30:44 PM PDT 24 |
| Peak memory | 204360 kb |
| Host | smart-586e512b-c285-4d2d-bd39-dee56a7d38bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125205558 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_same_csr_ou tstanding.1125205558 |
| Directory | /workspace/8.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/8.i2c_tl_errors.2290656157 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 468368709 ps |
| CPU time | 2.28 seconds |
| Started | Jul 19 04:30:40 PM PDT 24 |
| Finished | Jul 19 04:30:48 PM PDT 24 |
| Peak memory | 204508 kb |
| Host | smart-2ee0d43e-8a38-49ba-a5c0-5c59544064ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290656157 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_errors.2290656157 |
| Directory | /workspace/8.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.504473519 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 1301302950 ps |
| CPU time | 2.14 seconds |
| Started | Jul 19 04:30:40 PM PDT 24 |
| Finished | Jul 19 04:30:48 PM PDT 24 |
| Peak memory | 204472 kb |
| Host | smart-aef94178-53fb-45e4-b1a3-1a4a4d04f5d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504473519 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_intg_err.504473519 |
| Directory | /workspace/8.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.1335585032 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 61488892 ps |
| CPU time | 0.72 seconds |
| Started | Jul 19 04:30:38 PM PDT 24 |
| Finished | Jul 19 04:30:42 PM PDT 24 |
| Peak memory | 204408 kb |
| Host | smart-2c6a2158-ceb2-4221-bbbb-3554fc500cbc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335585032 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 9.i2c_csr_mem_rw_with_rand_reset.1335585032 |
| Directory | /workspace/9.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.i2c_csr_rw.3366659754 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 48401120 ps |
| CPU time | 0.69 seconds |
| Started | Jul 19 04:30:38 PM PDT 24 |
| Finished | Jul 19 04:30:42 PM PDT 24 |
| Peak memory | 204328 kb |
| Host | smart-a73b1c5b-6ae5-44c4-b9f4-c8e90794713f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366659754 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_rw.3366659754 |
| Directory | /workspace/9.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.i2c_intr_test.674896863 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 17948043 ps |
| CPU time | 0.7 seconds |
| Started | Jul 19 04:30:39 PM PDT 24 |
| Finished | Jul 19 04:30:44 PM PDT 24 |
| Peak memory | 204288 kb |
| Host | smart-d9c53d30-e22a-46a2-afce-6d4869beb996 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674896863 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_intr_test.674896863 |
| Directory | /workspace/9.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.758803629 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 205612620 ps |
| CPU time | 1.26 seconds |
| Started | Jul 19 04:30:39 PM PDT 24 |
| Finished | Jul 19 04:30:44 PM PDT 24 |
| Peak memory | 204480 kb |
| Host | smart-6899ddef-a9c1-4619-9c1c-4ad7a3c64bad |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758803629 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_same_csr_out standing.758803629 |
| Directory | /workspace/9.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.i2c_tl_errors.4031878749 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 316204181 ps |
| CPU time | 1.92 seconds |
| Started | Jul 19 04:30:36 PM PDT 24 |
| Finished | Jul 19 04:30:39 PM PDT 24 |
| Peak memory | 204504 kb |
| Host | smart-39e17d6b-38cb-4060-95b6-408774e58d2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031878749 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_errors.4031878749 |
| Directory | /workspace/9.i2c_tl_errors/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |