Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.14	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	7	53	88.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	7	53	88.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	814995	1			T1	3		T2	16		T3	2
all_values[1]	814995	1			T1	3		T2	16		T3	2
all_values[2]	814995	1			T1	3		T2	16		T3	2
all_values[3]	814995	1			T1	3		T2	16		T3	2
all_values[4]	814995	1			T1	3		T2	16		T3	2
all_values[5]	814995	1			T1	3		T2	16		T3	2
all_values[6]	814995	1			T1	3		T2	16		T3	2
all_values[7]	814995	1			T1	3		T2	16		T3	2
all_values[8]	814995	1			T1	3		T2	16		T3	2
all_values[9]	814995	1			T1	3		T2	16		T3	2
all_values[10]	814995	1			T1	3		T2	16		T3	2
all_values[11]	814995	1			T1	3		T2	16		T3	2
all_values[12]	814995	1			T1	3		T2	16		T3	2
all_values[13]	814995	1			T1	3		T2	16		T3	2
all_values[14]	814995	1			T1	3		T2	16		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10048077

1

T1

39

T2

208

T3

26

auto[1]

2176848

1

T1

6

T2

32

T3

4

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11270845

1

T1

45

T2

240

T3

30

auto[1]

954080

1

T26

195557

T172

72

T33

262

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	7	53	88.33	7

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[3]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[5] , all_values[6]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[8]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	122111	1			T1	1		T4	1		T9	1
all_values[0]	auto[0]	auto[1]	3962	1			T26	466		T33	13		T232	1771
all_values[0]	auto[1]	auto[0]	635514	1			T1	2		T2	16		T3	2
all_values[0]	auto[1]	auto[1]	53408	1			T26	12571		T172	4		T33	5
all_values[1]	auto[0]	auto[0]	755866	1			T1	3		T2	16		T3	2
all_values[1]	auto[0]	auto[1]	58638	1			T26	13030		T33	16		T232	25015
all_values[1]	auto[1]	auto[0]	351	1			T43	1		T107	27		T275	9
all_values[1]	auto[1]	auto[1]	140	1			T26	3		T33	2		T232	3
all_values[2]	auto[0]	auto[0]	755991	1			T1	3		T2	16		T3	2
all_values[2]	auto[0]	auto[1]	58656	1			T26	13031		T172	4		T33	17
all_values[2]	auto[1]	auto[0]	189	1			T7	1		T233	1		T234	2
all_values[2]	auto[1]	auto[1]	159	1			T26	6		T172	2		T33	1
all_values[3]	auto[0]	auto[0]	749285	1			T1	3		T2	16		T3	2
all_values[3]	auto[0]	auto[1]	65517	1			T26	13033		T172	4		T33	14
all_values[3]	auto[1]	auto[1]	193	1			T26	6		T172	2		T33	2
all_values[4]	auto[0]	auto[0]	749253	1			T1	3		T2	16		T3	2
all_values[4]	auto[0]	auto[1]	65572	1			T26	13030		T172	5		T33	15
all_values[4]	auto[1]	auto[0]	20	1			T258	1		T260	1		T276	1
all_values[4]	auto[1]	auto[1]	150	1			T26	3		T172	1		T33	2
all_values[5]	auto[0]	auto[0]	749296	1			T1	3		T2	16		T3	2
all_values[5]	auto[0]	auto[1]	65523	1			T26	13033		T172	2		T33	14
all_values[5]	auto[1]	auto[1]	176	1			T26	6		T172	3		T33	4
all_values[6]	auto[0]	auto[0]	749269	1			T1	3		T2	16		T3	2
all_values[6]	auto[0]	auto[1]	65555	1			T26	13028		T172	4		T33	14
all_values[6]	auto[1]	auto[1]	171	1			T26	5		T172	2		T33	3
all_values[7]	auto[0]	auto[0]	720116	1			T1	2		T2	16		T3	2
all_values[7]	auto[0]	auto[1]	63525	1			T26	12831		T33	15		T232	24739
all_values[7]	auto[1]	auto[0]	29175	1			T1	1		T15	49		T16	58
all_values[7]	auto[1]	auto[1]	2179	1			T26	207		T33	3		T232	281
all_values[8]	auto[0]	auto[0]	749269	1			T1	3		T2	16		T3	2
all_values[8]	auto[0]	auto[1]	65540	1			T26	13031		T172	2		T33	18
all_values[8]	auto[1]	auto[1]	186	1			T26	7		T172	4		T232	1
all_values[9]	auto[0]	auto[0]	166345	1			T1	2		T2	16		T3	2
all_values[9]	auto[0]	auto[1]	6853	1			T26	541		T172	4		T33	16
all_values[9]	auto[1]	auto[0]	582927	1			T1	1		T4	1		T7	1
all_values[9]	auto[1]	auto[1]	58870	1			T26	12497		T172	2		T33	2
all_values[10]	auto[0]	auto[0]	749295	1			T1	3		T2	16		T3	2
all_values[10]	auto[0]	auto[1]	65568	1			T26	13035		T172	4		T33	17
all_values[10]	auto[1]	auto[1]	132	1			T26	3		T172	2		T33	1
all_values[11]	auto[0]	auto[0]	2370	1			T1	1		T4	1		T9	1
all_values[11]	auto[0]	auto[1]	260	1			T26	13		T33	13		T232	16
all_values[11]	auto[1]	auto[0]	756363	1			T1	2		T2	16		T3	2
all_values[11]	auto[1]	auto[1]	56002	1			T26	13026		T172	4		T33	3
all_values[12]	auto[0]	auto[0]	749222	1			T1	3		T2	16		T3	2
all_values[12]	auto[0]	auto[1]	65572	1			T26	13033		T172	3		T33	15
all_values[12]	auto[1]	auto[0]	63	1			T64	1		T277	1		T278	1
all_values[12]	auto[1]	auto[1]	138	1			T26	5		T172	3		T33	2
all_values[13]	auto[0]	auto[0]	749285	1			T1	3		T2	16		T3	2
all_values[13]	auto[0]	auto[1]	65543	1			T26	13035		T172	4		T33	16
all_values[13]	auto[1]	auto[1]	167	1			T26	4		T172	2		T33	1
all_values[14]	auto[0]	auto[0]	749270	1			T1	3		T2	16		T3	2
all_values[14]	auto[0]	auto[1]	65550	1			T26	13031		T172	4		T33	15
all_values[14]	auto[1]	auto[1]	175	1			T26	7		T172	1		T33	3