Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	814995	1			T1	3		T2	16		T3	2
all_pins[1]	814995	1			T1	3		T2	16		T3	2
all_pins[2]	814995	1			T1	3		T2	16		T3	2
all_pins[3]	814995	1			T1	3		T2	16		T3	2
all_pins[4]	814995	1			T1	3		T2	16		T3	2
all_pins[5]	814995	1			T1	3		T2	16		T3	2
all_pins[6]	814995	1			T1	3		T2	16		T3	2
all_pins[7]	814995	1			T1	3		T2	16		T3	2
all_pins[8]	814995	1			T1	3		T2	16		T3	2
all_pins[9]	814995	1			T1	3		T2	16		T3	2
all_pins[10]	814995	1			T1	3		T2	16		T3	2
all_pins[11]	814995	1			T1	3		T2	16		T3	2
all_pins[12]	814995	1			T1	3		T2	16		T3	2
all_pins[13]	814995	1			T1	3		T2	16		T3	2
all_pins[14]	814995	1			T1	3		T2	16		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	10054146	1			T1	39		T2	208		T3	26
values[0x1]	2170779	1			T1	6		T2	32		T3	4
transitions[0x0=>0x1]	2170025	1			T1	6		T2	32		T3	4
transitions[0x1=>0x0]	2168720	1			T1	5		T2	31		T3	3

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	129806	1			T1	1		T4	1		T9	1
all_pins[0]	values[0x1]	685189	1			T1	2		T2	16		T3	2
all_pins[0]	transitions[0x0=>0x1]	684736	1			T1	2		T2	16		T3	2
all_pins[0]	transitions[0x1=>0x0]	47	1			T268	2		T232	1		T34	1
all_pins[1]	values[0x0]	814495	1			T1	3		T2	16		T3	2
all_pins[1]	values[0x1]	500	1			T43	1		T107	35		T26	2
all_pins[1]	transitions[0x0=>0x1]	483	1			T43	1		T107	35		T26	2
all_pins[1]	transitions[0x1=>0x0]	118	1			T7	1		T277	1		T278	1
all_pins[2]	values[0x0]	814860	1			T1	3		T2	16		T3	2
all_pins[2]	values[0x1]	135	1			T7	1		T277	1		T278	1
all_pins[2]	transitions[0x0=>0x1]	112	1			T7	1		T277	1		T278	1
all_pins[2]	transitions[0x1=>0x0]	89	1			T172	2		T232	1		T34	1
all_pins[3]	values[0x0]	814883	1			T1	3		T2	16		T3	2
all_pins[3]	values[0x1]	112	1			T26	1		T172	2		T232	3
all_pins[3]	transitions[0x0=>0x1]	85	1			T26	1		T172	1		T232	2
all_pins[3]	transitions[0x1=>0x0]	74	1			T26	1		T258	2		T260	1
all_pins[4]	values[0x0]	814894	1			T1	3		T2	16		T3	2
all_pins[4]	values[0x1]	101	1			T26	1		T258	2		T260	1
all_pins[4]	transitions[0x0=>0x1]	83	1			T258	2		T260	1		T276	1
all_pins[4]	transitions[0x1=>0x0]	71	1			T26	3		T172	1		T33	3
all_pins[5]	values[0x0]	814906	1			T1	3		T2	16		T3	2
all_pins[5]	values[0x1]	89	1			T26	4		T172	1		T33	4
all_pins[5]	transitions[0x0=>0x1]	68	1			T26	4		T172	1		T33	1
all_pins[5]	transitions[0x1=>0x0]	60	1			T26	4		T172	1		T232	1
all_pins[6]	values[0x0]	814914	1			T1	3		T2	16		T3	2
all_pins[6]	values[0x1]	81	1			T26	4		T172	1		T33	3
all_pins[6]	transitions[0x0=>0x1]	64	1			T26	4		T172	1		T33	2
all_pins[6]	transitions[0x1=>0x0]	34193	1			T1	1		T15	51		T16	67
all_pins[7]	values[0x0]	780785	1			T1	2		T2	16		T3	2
all_pins[7]	values[0x1]	34210	1			T1	1		T15	51		T16	67
all_pins[7]	transitions[0x0=>0x1]	34183	1			T1	1		T15	51		T16	67
all_pins[7]	transitions[0x1=>0x0]	67	1			T26	1		T232	1		T34	3
all_pins[8]	values[0x0]	814901	1			T1	3		T2	16		T3	2
all_pins[8]	values[0x1]	94	1			T26	5		T232	1		T34	3
all_pins[8]	transitions[0x0=>0x1]	71	1			T26	4		T232	1		T34	2
all_pins[8]	transitions[0x1=>0x0]	641733	1			T1	1		T4	1		T7	1
all_pins[9]	values[0x0]	173239	1			T1	2		T2	16		T3	2
all_pins[9]	values[0x1]	641756	1			T1	1		T4	1		T7	1
all_pins[9]	transitions[0x0=>0x1]	641742	1			T1	1		T4	1		T7	1
all_pins[9]	transitions[0x1=>0x0]	55	1			T26	1		T172	1		T232	1
all_pins[10]	values[0x0]	814926	1			T1	3		T2	16		T3	2
all_pins[10]	values[0x1]	69	1			T26	2		T172	1		T232	1
all_pins[10]	transitions[0x0=>0x1]	49	1			T26	2		T232	1		T34	2
all_pins[10]	transitions[0x1=>0x0]	808127	1			T1	2		T2	16		T3	2
all_pins[11]	values[0x0]	6848	1			T1	1		T4	1		T9	1
all_pins[11]	values[0x1]	808147	1			T1	2		T2	16		T3	2
all_pins[11]	transitions[0x0=>0x1]	808116	1			T1	2		T2	16		T3	2
all_pins[11]	transitions[0x1=>0x0]	98	1			T64	1		T65	1		T26	3
all_pins[12]	values[0x0]	814866	1			T1	3		T2	16		T3	2
all_pins[12]	values[0x1]	129	1			T64	1		T277	1		T278	1
all_pins[12]	transitions[0x0=>0x1]	117	1			T64	1		T277	1		T278	1
all_pins[12]	transitions[0x1=>0x0]	59	1			T26	1		T172	1		T34	1
all_pins[13]	values[0x0]	814924	1			T1	3		T2	16		T3	2
all_pins[13]	values[0x1]	71	1			T26	2		T172	1		T33	1
all_pins[13]	transitions[0x0=>0x1]	60	1			T26	2		T33	1		T34	1
all_pins[13]	transitions[0x1=>0x0]	85	1			T26	4		T33	2		T232	2
all_pins[14]	values[0x0]	814899	1			T1	3		T2	16		T3	2
all_pins[14]	values[0x1]	96	1			T26	4		T172	1		T33	2
all_pins[14]	transitions[0x0=>0x1]	56	1			T26	3		T232	1		T34	3
all_pins[14]	transitions[0x1=>0x0]	683844	1			T1	1		T2	15		T3	1