Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	357	1			T26	11		T172	4		T33	4
all_values[1]	357	1			T26	11		T172	4		T33	4
all_values[2]	357	1			T26	11		T172	4		T33	4
all_values[3]	357	1			T26	11		T172	4		T33	4
all_values[4]	357	1			T26	11		T172	4		T33	4
all_values[5]	357	1			T26	11		T172	4		T33	4
all_values[6]	357	1			T26	11		T172	4		T33	4
all_values[7]	357	1			T26	11		T172	4		T33	4
all_values[8]	357	1			T26	11		T172	4		T33	4
all_values[9]	357	1			T26	11		T172	4		T33	4
all_values[10]	357	1			T26	11		T172	4		T33	4
all_values[11]	357	1			T26	11		T172	4		T33	4
all_values[12]	357	1			T26	11		T172	4		T33	4
all_values[13]	357	1			T26	11		T172	4		T33	4
all_values[14]	357	1			T26	11		T172	4		T33	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2878

1

T26

71

T172

24

T33

25

auto[1]

2477

1

T26

94

T172

36

T33

35

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

908

1

T26

25

T172

14

T33

8

auto[1]

4447

1

T26

140

T172

46

T33

52

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3140

1

T26

98

T172

37

T33

35

auto[1]

2215

1

T26

67

T172

23

T33

25

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	39	1			T282	5		T120	1		T283	1
all_values[0]	auto[0]	auto[0]	auto[1]	70	1			T26	3		T172	1		T232	1
all_values[0]	auto[0]	auto[1]	auto[0]	27	1			T26	2		T172	2		T282	6
all_values[0]	auto[0]	auto[1]	auto[1]	70	1			T26	2		T33	1		T232	1
all_values[0]	auto[1]	auto[0]	auto[1]	82	1			T26	3		T33	1		T34	3
all_values[0]	auto[1]	auto[1]	auto[1]	69	1			T26	1		T172	1		T33	2
all_values[1]	auto[0]	auto[0]	auto[0]	49	1			T26	1		T172	1		T34	2
all_values[1]	auto[0]	auto[0]	auto[1]	83	1			T26	2		T33	2		T232	2
all_values[1]	auto[0]	auto[1]	auto[0]	33	1			T26	4		T172	3		T232	2
all_values[1]	auto[0]	auto[1]	auto[1]	60	1			T26	1		T34	2		T282	3
all_values[1]	auto[1]	auto[0]	auto[1]	80	1			T26	2		T33	1		T232	2
all_values[1]	auto[1]	auto[1]	auto[1]	52	1			T26	1		T33	1		T232	1
all_values[2]	auto[0]	auto[0]	auto[0]	40	1			T26	1		T34	1		T282	1
all_values[2]	auto[0]	auto[0]	auto[1]	69	1			T26	2		T172	1		T232	1
all_values[2]	auto[0]	auto[1]	auto[0]	15	1			T26	1		T282	1		T284	4
all_values[2]	auto[0]	auto[1]	auto[1]	74	1			T26	1		T172	1		T33	3
all_values[2]	auto[1]	auto[0]	auto[1]	75	1			T26	4		T172	1		T34	2
all_values[2]	auto[1]	auto[1]	auto[1]	84	1			T26	2		T172	1		T33	1
all_values[3]	auto[0]	auto[0]	auto[0]	40	1			T33	2		T34	1		T284	2
all_values[3]	auto[0]	auto[0]	auto[1]	56	1			T26	4		T33	1		T232	1
all_values[3]	auto[0]	auto[1]	auto[0]	24	1			T34	3		T282	1		T120	1
all_values[3]	auto[0]	auto[1]	auto[1]	86	1			T26	2		T172	2		T232	1
all_values[3]	auto[1]	auto[0]	auto[1]	69	1			T26	1		T33	1		T232	2
all_values[3]	auto[1]	auto[1]	auto[1]	82	1			T26	4		T172	2		T232	3
all_values[4]	auto[0]	auto[0]	auto[0]	31	1			T26	2		T33	1		T232	1
all_values[4]	auto[0]	auto[0]	auto[1]	60	1			T232	1		T34	3		T282	2
all_values[4]	auto[0]	auto[1]	auto[0]	22	1			T26	3		T120	2		T121	1
all_values[4]	auto[0]	auto[1]	auto[1]	94	1			T26	3		T172	3		T33	1
all_values[4]	auto[1]	auto[0]	auto[1]	82	1			T26	3		T33	1		T232	3
all_values[4]	auto[1]	auto[1]	auto[1]	68	1			T172	1		T33	1		T34	1
all_values[5]	auto[0]	auto[0]	auto[0]	39	1			T34	1		T282	1		T283	2
all_values[5]	auto[0]	auto[0]	auto[1]	68	1			T26	3		T172	1		T232	1
all_values[5]	auto[0]	auto[1]	auto[0]	32	1			T172	1		T34	3		T120	1
all_values[5]	auto[0]	auto[1]	auto[1]	73	1			T26	3		T33	2		T232	3
all_values[5]	auto[1]	auto[0]	auto[1]	79	1			T26	1		T232	2		T34	2
all_values[5]	auto[1]	auto[1]	auto[1]	66	1			T26	4		T172	2		T33	2
all_values[6]	auto[0]	auto[0]	auto[0]	28	1			T120	1		T121	2		T285	1
all_values[6]	auto[0]	auto[0]	auto[1]	83	1			T26	1		T172	1		T232	2
all_values[6]	auto[0]	auto[1]	auto[0]	19	1			T26	5		T33	1		T120	1
all_values[6]	auto[0]	auto[1]	auto[1]	80	1			T26	1		T172	1		T33	2
all_values[6]	auto[1]	auto[0]	auto[1]	89	1			T26	1		T172	1		T232	3
all_values[6]	auto[1]	auto[1]	auto[1]	58	1			T26	3		T172	1		T33	1
all_values[7]	auto[0]	auto[0]	auto[0]	49	1			T172	2		T282	1		T121	1
all_values[7]	auto[0]	auto[0]	auto[1]	77	1			T26	4		T33	2		T232	4
all_values[7]	auto[0]	auto[1]	auto[0]	18	1			T26	1		T172	2		T34	1
all_values[7]	auto[0]	auto[1]	auto[1]	72	1			T26	2		T232	1		T34	5
all_values[7]	auto[1]	auto[0]	auto[1]	77	1			T26	2		T33	1		T232	1
all_values[7]	auto[1]	auto[1]	auto[1]	64	1			T26	2		T33	1		T232	1
all_values[8]	auto[0]	auto[0]	auto[0]	34	1			T282	1		T283	1		T121	1
all_values[8]	auto[0]	auto[0]	auto[1]	75	1			T26	1		T172	3		T33	1
all_values[8]	auto[0]	auto[1]	auto[0]	15	1			T26	1		T232	1		T120	1
all_values[8]	auto[0]	auto[1]	auto[1]	72	1			T26	2		T33	2		T232	1
all_values[8]	auto[1]	auto[0]	auto[1]	88	1			T26	3		T34	2		T282	3
all_values[8]	auto[1]	auto[1]	auto[1]	73	1			T26	4		T172	1		T33	1
all_values[9]	auto[0]	auto[0]	auto[0]	32	1			T232	1		T284	2		T121	2
all_values[9]	auto[0]	auto[0]	auto[1]	77	1			T26	5		T172	2		T232	2
all_values[9]	auto[0]	auto[1]	auto[0]	22	1			T26	1		T34	1		T286	1
all_values[9]	auto[0]	auto[1]	auto[1]	73	1			T33	2		T232	2		T34	2
all_values[9]	auto[1]	auto[0]	auto[1]	84	1			T26	2		T172	1		T33	1
all_values[9]	auto[1]	auto[1]	auto[1]	69	1			T26	3		T172	1		T33	1
all_values[10]	auto[0]	auto[0]	auto[0]	49	1			T232	2		T34	1		T283	1
all_values[10]	auto[0]	auto[0]	auto[1]	70	1			T26	2		T172	2		T33	3
all_values[10]	auto[0]	auto[1]	auto[0]	24	1			T26	1		T121	1		T285	1
all_values[10]	auto[0]	auto[1]	auto[1]	82	1			T26	5		T232	3		T34	3
all_values[10]	auto[1]	auto[0]	auto[1]	67	1			T26	1		T172	1		T33	1
all_values[10]	auto[1]	auto[1]	auto[1]	65	1			T26	2		T172	1		T232	2
all_values[11]	auto[0]	auto[0]	auto[0]	30	1			T172	1		T34	2		T120	3
all_values[11]	auto[0]	auto[0]	auto[1]	77	1			T172	1		T33	1		T232	2
all_values[11]	auto[0]	auto[1]	auto[0]	23	1			T172	1		T33	2		T232	1
all_values[11]	auto[0]	auto[1]	auto[1]	77	1			T26	5		T232	1		T34	2
all_values[11]	auto[1]	auto[0]	auto[1]	86	1			T26	1		T172	1		T33	1
all_values[11]	auto[1]	auto[1]	auto[1]	64	1			T26	5		T232	2		T34	2
all_values[12]	auto[0]	auto[0]	auto[0]	33	1			T282	1		T283	1		T121	1
all_values[12]	auto[0]	auto[0]	auto[1]	91	1			T26	1		T33	1		T232	2
all_values[12]	auto[0]	auto[1]	auto[0]	28	1			T26	1		T33	1		T232	2
all_values[12]	auto[0]	auto[1]	auto[1]	67	1			T26	4		T172	1		T232	2
all_values[12]	auto[1]	auto[0]	auto[1]	82	1			T26	2		T172	2		T33	1
all_values[12]	auto[1]	auto[1]	auto[1]	56	1			T26	3		T172	1		T33	1
all_values[13]	auto[0]	auto[0]	auto[0]	42	1			T33	1		T232	2		T34	1
all_values[13]	auto[0]	auto[0]	auto[1]	82	1			T26	7		T172	1		T232	1
all_values[13]	auto[0]	auto[1]	auto[0]	23	1			T285	2		T287	2		T288	1
all_values[13]	auto[0]	auto[1]	auto[1]	64	1			T26	1		T33	2		T34	2
all_values[13]	auto[1]	auto[0]	auto[1]	82	1			T26	1		T232	4		T282	6
all_values[13]	auto[1]	auto[1]	auto[1]	64	1			T26	2		T172	3		T33	1
all_values[14]	auto[0]	auto[0]	auto[0]	27	1			T283	1		T289	1		T287	1
all_values[14]	auto[0]	auto[0]	auto[1]	73	1			T26	2		T232	1		T34	2
all_values[14]	auto[0]	auto[1]	auto[0]	21	1			T26	1		T172	1		T232	2
all_values[14]	auto[0]	auto[1]	auto[1]	77	1			T26	4		T172	2		T33	1
all_values[14]	auto[1]	auto[0]	auto[1]	83	1			T26	3		T33	1		T232	1
all_values[14]	auto[1]	auto[1]	auto[1]	76	1			T26	1		T172	1		T33	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal