Group : i2c_env_pkg::i2c_interrupts_cg
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Group : i2c_env_pkg::i2c_interrupts_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
i2c_env_pkg.interrupts_cg 100.00 1 100 1 64 64




Group Instance : i2c_env_pkg.interrupts_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance i2c_env_pkg.interrupts_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 45 0 45 100.00


Variables for Group Instance i2c_env_pkg.interrupts_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_acq_stretch 2 0 2 100.00 100 1 1 2
cp_acq_stretch_test 1 0 1 100.00 100 1 1 2
cp_acq_threshold 2 0 2 100.00 100 1 1 2
cp_acq_threshold_test 1 0 1 100.00 100 1 1 2
cp_cmd_complete 2 0 2 100.00 100 1 1 2
cp_cmd_complete_test 1 0 1 100.00 100 1 1 2
cp_fmt_threshold 2 0 2 100.00 100 1 1 2
cp_fmt_threshold_test 1 0 1 100.00 100 1 1 2
cp_host_timeout 2 0 2 100.00 100 1 1 2
cp_host_timeout_test 1 0 1 100.00 100 1 1 2
cp_nak 2 0 2 100.00 100 1 1 2
cp_nak_test 1 0 1 100.00 100 1 1 2
cp_rx_overflow 2 0 2 100.00 100 1 1 2
cp_rx_overflow_test 1 0 1 100.00 100 1 1 2
cp_rx_threshold 2 0 2 100.00 100 1 1 2
cp_rx_threshold_test 1 0 1 100.00 100 1 1 2
cp_scl_interference 2 0 2 100.00 100 1 1 2
cp_scl_interference_test 1 0 1 100.00 100 1 1 2
cp_sda_interference 2 0 2 100.00 100 1 1 2
cp_sda_interference_test 1 0 1 100.00 100 1 1 2
cp_sda_unstable 2 0 2 100.00 100 1 1 2
cp_sda_unstable_test 1 0 1 100.00 100 1 1 2
cp_stretch_timeout 2 0 2 100.00 100 1 1 2
cp_stretch_timeout_test 1 0 1 100.00 100 1 1 2
cp_tx_stretch 2 0 2 100.00 100 1 1 2
cp_tx_stretch_test 1 0 1 100.00 100 1 1 2
cp_tx_threshold 2 0 2 100.00 100 1 1 2
cp_tx_threshold_test 1 0 1 100.00 100 1 1 2
cp_unexp_stop 2 0 2 100.00 100 1 1 2
cp_unexp_stop_test 1 0 1 100.00 100 1 1 2


Summary for Variable cp_acq_stretch

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_acq_stretch

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 761322 1 T1 3 T2 4 T3 457
auto[1] 414 1 T19 1 T51 1 T65 1



Summary for Variable cp_acq_stretch_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for cp_acq_stretch_test

Excluded/Illegal bins
NAMECOUNTSTATUS
dis 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 152 1 T19 1 T106 3 T152 1



Summary for Variable cp_acq_threshold

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_acq_threshold

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 761084 1 T1 3 T2 4 T3 457
auto[1] 454 1 T5 1 T143 1 T273 1



Summary for Variable cp_acq_threshold_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for cp_acq_threshold_test

Excluded/Illegal bins
NAMECOUNTSTATUS
dis 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 171 1 T19 1 T106 1 T152 2



Summary for Variable cp_cmd_complete

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_cmd_complete

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 196532 1 T1 3 T2 3 T3 449
auto[1] 565379 1 T2 1 T3 8 T6 9



Summary for Variable cp_cmd_complete_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for cp_cmd_complete_test

Excluded/Illegal bins
NAMECOUNTSTATUS
dis 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 164 1 T19 2 T106 1 T152 1



Summary for Variable cp_fmt_threshold

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_fmt_threshold

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 115316 1 T1 3 T2 2 T3 360
auto[1] 642317 1 T2 2 T3 97 T4 3



Summary for Variable cp_fmt_threshold_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for cp_fmt_threshold_test

Excluded/Illegal bins
NAMECOUNTSTATUS
dis 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 163 1 T106 2 T153 3 T238 2



Summary for Variable cp_host_timeout

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_host_timeout

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 761349 1 T1 3 T2 4 T3 457
auto[1] 439 1 T19 5 T106 12 T152 4



Summary for Variable cp_host_timeout_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for cp_host_timeout_test

Excluded/Illegal bins
NAMECOUNTSTATUS
dis 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 166 1 T19 2 T106 2 T152 1



Summary for Variable cp_nak

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_nak

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 761521 1 T1 3 T2 4 T3 457
auto[1] 464 1 T21 2 T144 1 T19 1



Summary for Variable cp_nak_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for cp_nak_test

Excluded/Illegal bins
NAMECOUNTSTATUS
dis 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 165 1 T19 1 T106 2 T152 3



Summary for Variable cp_rx_overflow

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_rx_overflow

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 761182 1 T1 3 T2 4 T3 457
auto[1] 478 1 T106 3 T152 17 T153 8



Summary for Variable cp_rx_overflow_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for cp_rx_overflow_test

Excluded/Illegal bins
NAMECOUNTSTATUS
dis 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 176 1 T106 2 T152 1 T153 3



Summary for Variable cp_rx_threshold

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_rx_threshold

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 760783 1 T1 3 T2 4 T3 457
auto[1] 815 1 T15 26 T161 13 T19 37



Summary for Variable cp_rx_threshold_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for cp_rx_threshold_test

Excluded/Illegal bins
NAMECOUNTSTATUS
dis 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 168 1 T19 3 T106 1 T152 2



Summary for Variable cp_scl_interference

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_scl_interference

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 757396 1 T1 3 T2 4 T3 457
auto[1] 424 1 T19 1 T152 4 T238 6



Summary for Variable cp_scl_interference_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for cp_scl_interference_test

Excluded/Illegal bins
NAMECOUNTSTATUS
dis 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 165 1 T19 1 T106 1 T152 1



Summary for Variable cp_sda_interference

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_sda_interference

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 757383 1 T1 3 T2 4 T3 457
auto[1] 428 1 T19 10 T106 7 T152 10



Summary for Variable cp_sda_interference_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for cp_sda_interference_test

Excluded/Illegal bins
NAMECOUNTSTATUS
dis 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 174 1 T19 2 T106 2 T152 3



Summary for Variable cp_sda_unstable

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_sda_unstable

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 757543 1 T1 3 T2 4 T3 457
auto[1] 457 1 T19 6 T106 6 T152 1



Summary for Variable cp_sda_unstable_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for cp_sda_unstable_test

Excluded/Illegal bins
NAMECOUNTSTATUS
dis 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 163 1 T19 2 T106 2 T152 1



Summary for Variable cp_stretch_timeout

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_stretch_timeout

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 730019 1 T1 3 T2 3 T3 373
auto[1] 27862 1 T2 1 T3 84 T6 148



Summary for Variable cp_stretch_timeout_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for cp_stretch_timeout_test

Excluded/Illegal bins
NAMECOUNTSTATUS
dis 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 173 1 T19 2 T106 1 T152 3



Summary for Variable cp_tx_stretch

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_tx_stretch

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 761350 1 T1 3 T2 4 T3 457
auto[1] 349 1 T19 14 T106 9 T152 4



Summary for Variable cp_tx_stretch_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for cp_tx_stretch_test

Excluded/Illegal bins
NAMECOUNTSTATUS
dis 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 156 1 T19 3 T106 2 T152 2



Summary for Variable cp_tx_threshold

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_tx_threshold

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 5132 1 T1 3 T2 2 T3 6
auto[1] 752319 1 T2 2 T3 451 T4 1



Summary for Variable cp_tx_threshold_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for cp_tx_threshold_test

Excluded/Illegal bins
NAMECOUNTSTATUS
dis 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 172 1 T19 3 T152 2 T153 2



Summary for Variable cp_unexp_stop

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_unexp_stop

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 761459 1 T1 3 T2 4 T3 457
auto[1] 381 1 T19 10 T152 4 T153 2



Summary for Variable cp_unexp_stop_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for cp_unexp_stop_test

Excluded/Illegal bins
NAMECOUNTSTATUS
dis 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 163 1 T19 1 T152 2 T153 4

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%