Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	35578383	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

9983785

1

T1

32

T2

13910

T3

13367

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	44720902	1			T1	97		T2	28627		T3	112785
values[0x0]	420581	1			T1	39		T2	77		T3	957
values[0x1]	420685	1			T1	53		T2	88		T3	1019

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	24960171	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

20601997

1

T1

93

T2

17078

T3

45441

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	172844	1			T2	46		T3	442		T5	2
valid_sources[0x01]	179719	1			T2	101		T3	406		T6	27
valid_sources[0x02]	181592	1			T2	65		T3	458		T6	1009
valid_sources[0x03]	197313	1			T2	67		T3	434		T6	1021
valid_sources[0x04]	204493	1			T2	79		T3	440		T6	526
valid_sources[0x05]	171085	1			T2	158		T3	431		T4	1
valid_sources[0x06]	175638	1			T2	101		T3	470		T6	8
valid_sources[0x07]	170481	1			T2	63		T3	411		T6	1013
valid_sources[0x08]	175954	1			T2	116		T3	426		T6	20
valid_sources[0x09]	213108	1			T2	113		T3	493		T5	4
valid_sources[0x0a]	187155	1			T2	121		T3	477		T5	4
valid_sources[0x0b]	177879	1			T2	104		T3	455		T5	1
valid_sources[0x0c]	184694	1			T2	109		T3	453		T5	1
valid_sources[0x0d]	168601	1			T2	146		T3	455		T6	516
valid_sources[0x0e]	161897	1			T2	106		T3	498		T6	517
valid_sources[0x0f]	183133	1			T2	71		T3	442		T5	4
valid_sources[0x10]	168984	1			T2	84		T3	519		T6	506
valid_sources[0x11]	173003	1			T2	120		T3	473		T5	2
valid_sources[0x12]	184767	1			T2	130		T3	466		T6	8
valid_sources[0x13]	179860	1			T2	73		T3	432		T5	1
valid_sources[0x14]	164510	1			T2	147		T3	457		T5	2
valid_sources[0x15]	169521	1			T2	36		T3	444		T6	1023
valid_sources[0x16]	173350	1			T2	141		T3	424		T5	5
valid_sources[0x17]	190126	1			T2	146		T3	477		T6	522
valid_sources[0x18]	188787	1			T2	188		T3	434		T5	2
valid_sources[0x19]	201540	1			T2	240		T3	427		T5	1
valid_sources[0x1a]	176395	1			T2	122		T3	466		T5	1
valid_sources[0x1b]	168367	1			T2	97		T3	433		T4	2
valid_sources[0x1c]	171426	1			T2	92		T3	417		T6	517
valid_sources[0x1d]	178840	1			T2	91		T3	466		T5	1
valid_sources[0x1e]	181049	1			T2	43		T3	455		T6	519
valid_sources[0x1f]	188404	1			T2	81		T3	467		T6	512
valid_sources[0x20]	184317	1			T2	147		T3	461		T6	1523
valid_sources[0x21]	179190	1			T2	155		T3	432		T5	4
valid_sources[0x22]	177261	1			T2	73		T3	451		T5	3
valid_sources[0x23]	171938	1			T2	158		T3	446		T6	1024
valid_sources[0x24]	162798	1			T2	133		T3	417		T6	1029
valid_sources[0x25]	176528	1			T2	163		T3	439		T6	29
valid_sources[0x26]	174389	1			T2	98		T3	433		T6	504
valid_sources[0x27]	181163	1			T1	189		T2	199		T3	439
valid_sources[0x28]	182772	1			T2	135		T3	463		T4	1
valid_sources[0x29]	192829	1			T2	142		T3	493		T6	946
valid_sources[0x2a]	186231	1			T2	128		T3	463		T6	1007
valid_sources[0x2b]	169080	1			T2	135		T3	438		T6	1517
valid_sources[0x2c]	189817	1			T2	77		T3	486		T4	3
valid_sources[0x2d]	165987	1			T2	131		T3	444		T5	1
valid_sources[0x2e]	182858	1			T2	104		T3	427		T6	504
valid_sources[0x2f]	178963	1			T2	153		T3	429		T6	10
valid_sources[0x30]	191332	1			T2	85		T3	414		T5	5
valid_sources[0x31]	189149	1			T2	73		T3	452		T6	1506
valid_sources[0x32]	172746	1			T2	137		T3	445		T6	1474
valid_sources[0x33]	171282	1			T2	81		T3	412		T6	2016
valid_sources[0x34]	178826	1			T2	79		T3	429		T6	506
valid_sources[0x35]	169531	1			T2	114		T3	448		T6	516
valid_sources[0x36]	172471	1			T2	162		T3	405		T6	1509
valid_sources[0x37]	177147	1			T2	86		T3	457		T6	513
valid_sources[0x38]	170114	1			T2	126		T3	442		T4	4
valid_sources[0x39]	190849	1			T2	132		T3	443		T5	2
valid_sources[0x3a]	170888	1			T2	46		T3	449		T5	1
valid_sources[0x3b]	207131	1			T2	124		T3	437		T6	7
valid_sources[0x3c]	183784	1			T2	109		T3	464		T6	1014
valid_sources[0x3d]	171059	1			T2	99		T3	411		T6	16
valid_sources[0x3e]	178717	1			T2	59		T3	434		T6	516
valid_sources[0x3f]	166922	1			T2	44		T3	449		T5	1
valid_sources[0x40]	174145	1			T2	95		T3	411		T6	1024
valid_sources[0x41]	162988	1			T2	90		T3	451		T5	2
valid_sources[0x42]	180929	1			T2	174		T3	457		T6	1003
valid_sources[0x43]	189474	1			T2	131		T3	435		T5	1
valid_sources[0x44]	175904	1			T2	50		T3	469		T6	516
valid_sources[0x45]	166313	1			T2	84		T3	428		T5	4
valid_sources[0x46]	176451	1			T2	89		T3	432		T6	13
valid_sources[0x47]	172741	1			T2	131		T3	483		T6	518
valid_sources[0x48]	183492	1			T2	110		T3	458		T4	1
valid_sources[0x49]	178474	1			T2	103		T3	478		T5	1
valid_sources[0x4a]	175356	1			T2	67		T3	457		T5	3
valid_sources[0x4b]	186879	1			T2	95		T3	423		T6	514
valid_sources[0x4c]	197682	1			T2	116		T3	430		T5	2
valid_sources[0x4d]	163619	1			T2	141		T3	451		T6	29
valid_sources[0x4e]	193821	1			T2	85		T3	460		T5	1
valid_sources[0x4f]	174958	1			T2	117		T3	457		T5	5
valid_sources[0x50]	177521	1			T2	41		T3	430		T5	4
valid_sources[0x51]	172136	1			T2	164		T3	462		T6	18
valid_sources[0x52]	194367	1			T2	87		T3	440		T5	2
valid_sources[0x53]	182456	1			T2	49		T3	444		T6	1020
valid_sources[0x54]	185668	1			T2	115		T3	436		T6	519
valid_sources[0x55]	176354	1			T2	144		T3	467		T6	14
valid_sources[0x56]	168512	1			T2	83		T3	477		T5	4
valid_sources[0x57]	182472	1			T2	130		T3	472		T5	4
valid_sources[0x58]	208497	1			T2	107		T3	449		T6	2529
valid_sources[0x59]	165878	1			T2	90		T3	468		T5	5
valid_sources[0x5a]	185841	1			T2	122		T3	454		T6	1031
valid_sources[0x5b]	169007	1			T2	105		T3	473		T6	1524
valid_sources[0x5c]	176691	1			T2	232		T3	462		T6	516
valid_sources[0x5d]	167231	1			T2	135		T3	441		T6	441
valid_sources[0x5e]	170464	1			T2	92		T3	459		T5	4
valid_sources[0x5f]	197208	1			T2	100		T3	460		T4	1
valid_sources[0x60]	164846	1			T2	71		T3	446		T6	13
valid_sources[0x61]	183942	1			T2	137		T3	430		T6	509
valid_sources[0x62]	175809	1			T2	92		T3	477		T6	1031
valid_sources[0x63]	172839	1			T2	123		T3	456		T6	501
valid_sources[0x64]	177759	1			T2	118		T3	464		T6	512
valid_sources[0x65]	162864	1			T2	142		T3	428		T6	3
valid_sources[0x66]	175513	1			T2	175		T3	460		T6	1015
valid_sources[0x67]	168862	1			T2	83		T3	487		T5	2
valid_sources[0x68]	165259	1			T2	129		T3	471		T6	1025
valid_sources[0x69]	195071	1			T2	56		T3	415		T5	4
valid_sources[0x6a]	174524	1			T2	100		T3	446		T6	512
valid_sources[0x6b]	192619	1			T2	111		T3	424		T6	1015
valid_sources[0x6c]	155448	1			T2	134		T3	415		T6	10
valid_sources[0x6d]	198606	1			T2	55		T3	478		T5	2
valid_sources[0x6e]	174442	1			T2	151		T3	445		T5	1
valid_sources[0x6f]	190261	1			T2	73		T3	442		T6	25
valid_sources[0x70]	169591	1			T2	92		T3	460		T6	1019
valid_sources[0x71]	162481	1			T2	125		T3	391		T5	3
valid_sources[0x72]	168502	1			T2	122		T3	403		T5	1
valid_sources[0x73]	161952	1			T2	111		T3	440		T5	2
valid_sources[0x74]	170659	1			T2	92		T3	419		T5	1
valid_sources[0x75]	179301	1			T2	165		T3	459		T6	1519
valid_sources[0x76]	166805	1			T2	132		T3	480		T5	2
valid_sources[0x77]	177231	1			T2	156		T3	494		T5	5
valid_sources[0x78]	167418	1			T2	135		T3	416		T6	2528
valid_sources[0x79]	164317	1			T2	122		T3	439		T6	9
valid_sources[0x7a]	183247	1			T2	121		T3	384		T5	1
valid_sources[0x7b]	181400	1			T2	133		T3	458		T6	11
valid_sources[0x7c]	188297	1			T2	143		T3	469		T5	6
valid_sources[0x7d]	172815	1			T2	127		T3	422		T6	516
valid_sources[0x7e]	180186	1			T2	107		T3	465		T6	525
valid_sources[0x7f]	183099	1			T2	214		T3	439		T5	1
valid_sources[0x80]	178123	1			T2	74		T3	469		T6	13

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

9613485

1

T2

13775

T3

12613

T4

1

values[0x0]

all_enables

biggest_size

220438

1

T1

23

T2

63

T3

470

values[0x1]

all_enables

biggest_size

149862

1

T1

9

T2

72

T3

284