Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.48	100.00	100.00	93.91			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	405366923	0	0	0
ctrl_rd_A	405366923	2610	0	0
host_fifo_config_rd_A	405366923	4528	0	0
host_nack_handler_timeout_rd_A	405366923	1680	0	0
host_timeout_ctrl_rd_A	405366923	1592	0	0
intr_enable_rd_A	405366923	4657	0	0
ovrd_rd_A	405366923	2617	0	0
target_fifo_config_rd_A	405366923	1682	0	0
target_id_rd_A	405366923	1881	0	0
target_timeout_ctrl_rd_A	405366923	1682	0	0
timeout_ctrl_rd_A	405366923	1867	0	0
timing0_rd_A	405366923	1719	0	0
timing1_rd_A	405366923	1667	0	0
timing2_rd_A	405366923	1662	0	0
timing3_rd_A	405366923	1669	0	0
timing4_rd_A	405366923	1755	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405366923	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405366923	2610	0	0
T96	2280	24	0	0
T97	5678	102	0	0
T98	1876	13	0	0
T99	5610	48	0	0
T100	7405	162	0	0
T101	1965	13	0	0
T102	4119	3	0	0
T103	3170	6	0	0
T104	1410	32	0	0
T105	3913	28	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405366923	4528	0	0
T106	564272	196	0	0
T107	0	128	0	0
T108	0	174	0	0
T109	0	194	0	0
T110	0	112	0	0
T111	0	217	0	0
T112	0	152	0	0
T113	0	219	0	0
T114	0	142	0	0
T115	0	198	0	0
T116	92003	0	0	0
T117	167115	0	0	0
T118	24103	0	0	0
T119	204911	0	0	0
T120	1528	0	0	0
T121	31051	0	0	0
T122	48707	0	0	0
T123	17395	0	0	0
T124	105267	0	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405366923	1680	0	0
T96	2280	2	0	0
T97	5678	91	0	0
T98	1876	14	0	0
T99	5610	78	0	0
T100	7405	67	0	0
T101	1965	9	0	0
T104	1410	5	0	0
T105	3913	14	0	0
T125	5646	17	0	0
T126	7103	12	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405366923	1592	0	0
T96	2280	14	0	0
T97	5678	86	0	0
T98	1876	6	0	0
T99	5610	34	0	0
T100	7405	26	0	0
T102	4119	10	0	0
T103	3170	3	0	0
T104	1410	4	0	0
T105	3913	29	0	0
T125	5646	32	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405366923	4657	0	0
T96	0	55	0	0
T97	0	151	0	0
T98	0	70	0	0
T99	0	25	0	0
T100	0	339	0	0
T106	564272	6	0	0
T116	92003	0	0	0
T117	167115	0	0	0
T118	24103	0	0	0
T119	204911	0	0	0
T120	1528	0	0	0
T121	31051	0	0	0
T122	48707	0	0	0
T123	17395	0	0	0
T124	105267	0	0	0
T127	0	29	0	0
T128	0	17	0	0
T129	0	19	0	0
T130	0	15	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405366923	2617	0	0
T49	46777	0	0	0
T50	46788	0	0	0
T53	12117	0	0	0
T77	133198	0	0	0
T79	2202	50	0	0
T80	1933	0	0	0
T95	15506	0	0	0
T120	0	53	0	0
T131	0	47	0	0
T132	0	88	0	0
T133	0	50	0	0
T134	0	70	0	0
T135	0	29	0	0
T136	0	45	0	0
T137	0	44	0	0
T138	0	41	0	0
T139	16682	0	0	0
T140	16889	0	0	0
T141	59114	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405366923	1682	0	0
T96	2280	7	0	0
T97	5678	89	0	0
T98	1876	14	0	0
T99	5610	61	0	0
T100	7405	69	0	0
T101	1965	6	0	0
T102	4119	6	0	0
T104	1410	2	0	0
T105	3913	32	0	0
T125	5646	44	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405366923	1881	0	0
T96	2280	2	0	0
T97	5678	79	0	0
T98	1876	17	0	0
T99	5610	44	0	0
T100	7405	96	0	0
T101	1965	2	0	0
T105	3913	12	0	0
T125	5646	12	0	0
T126	7103	1	0	0
T142	1942	18	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405366923	1682	0	0
T96	2280	8	0	0
T97	5678	85	0	0
T98	1876	11	0	0
T99	5610	29	0	0
T100	7405	52	0	0
T101	1965	6	0	0
T102	4119	3	0	0
T103	3170	7	0	0
T104	1410	4	0	0
T105	3913	11	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405366923	1867	0	0
T96	2280	6	0	0
T97	5678	93	0	0
T98	1876	11	0	0
T99	5610	43	0	0
T100	7405	88	0	0
T101	1965	9	0	0
T102	4119	10	0	0
T103	3170	15	0	0
T104	1410	13	0	0
T105	3913	21	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405366923	1719	0	0
T96	2280	9	0	0
T97	5678	62	0	0
T98	1876	13	0	0
T99	5610	52	0	0
T100	7405	41	0	0
T101	1965	4	0	0
T102	4119	2	0	0
T103	3170	42	0	0
T104	1410	9	0	0
T105	3913	32	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405366923	1667	0	0
T96	2280	17	0	0
T97	5678	112	0	0
T98	1876	6	0	0
T99	5610	31	0	0
T100	7405	77	0	0
T101	1965	9	0	0
T102	4119	3	0	0
T104	1410	2	0	0
T105	3913	29	0	0
T125	5646	64	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405366923	1662	0	0
T96	2280	15	0	0
T97	5678	88	0	0
T98	1876	9	0	0
T99	5610	33	0	0
T100	7405	41	0	0
T101	1965	4	0	0
T103	3170	12	0	0
T104	1410	8	0	0
T105	3913	6	0	0
T125	5646	38	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405366923	1669	0	0
T96	2280	8	0	0
T97	5678	90	0	0
T98	1876	27	0	0
T99	5610	43	0	0
T100	7405	60	0	0
T101	1965	8	0	0
T103	3170	14	0	0
T104	1410	12	0	0
T105	3913	18	0	0
T125	5646	12	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405366923	1755	0	0
T96	2280	12	0	0
T97	5678	126	0	0
T98	1876	14	0	0
T99	5610	61	0	0
T100	7405	76	0	0
T101	1965	1	0	0
T102	4119	4	0	0
T103	3170	35	0	0
T104	1410	16	0	0
T105	3913	15	0	0