Unified Coverage Report :: Group :: i2c_env_pkg::i2c_status_cg

Group : i2c_env_pkg::i2c_status_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.status_cg	100.00	1	100	1	64	64

---

Group Instance : i2c_env_pkg.status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00

Variables for Group Instance i2c_env_pkg.status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_acqempty	2	0	2	100.00	100	1	1	2
cp_acqfull	2	0	2	100.00	100	1	1	2
cp_fmtempty	2	0	2	100.00	100	1	1	2
cp_fmtfull	2	0	2	100.00	100	1	1	2
cp_hostidle	2	0	2	100.00	100	1	1	2
cp_rxempty	2	0	2	100.00	100	1	1	2
cp_rxfull	2	0	2	100.00	100	1	1	2
cp_targetidle	2	0	2	100.00	100	1	1	2
cp_txempty	2	0	2	100.00	100	1	1	2
cp_txfull	2	0	2	100.00	100	1	1	2

Summary for Variable cp_acqempty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_acqempty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1352718

1

T1

323

T5

1

T7

1

auto[1]

35092167

1

T1

24

T3

20372

T4

12

---

Summary for Variable cp_acqfull

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_acqfull

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

36424714

1

T1

347

T3

20372

T4

12

auto[1]

20171

1

T55

207

T59

17

T60

527

---

Summary for Variable cp_fmtempty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_fmtempty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34167246

1

T3

19251

T6

15490

T8

22867

auto[1]

2277639

1

T1

347

T3

1121

T4

12

---

Summary for Variable cp_fmtfull

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_fmtfull

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29200580

1

T1

347

T3

20372

T4

12

auto[1]

7244305

1

T44

362

T19

44082

T155

54518

---

Summary for Variable cp_hostidle

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_hostidle

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34164238

1

T3

19251

T6

15490

T8

22867

auto[1]

2280647

1

T1

347

T3

1121

T4

12

---

Summary for Variable cp_rxempty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rxempty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5750204

1

T3

19755

T6

282

T8

22999

auto[1]

30694681

1

T1

347

T3

617

T4

12

---

Summary for Variable cp_rxfull

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rxfull

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

36396137

1

T1

347

T3

20031

T4

12

auto[1]

48748

1

T3

341

T8

385

T45

1

---

Summary for Variable cp_targetidle

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_targetidle

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1971968

1

T1

339

T5

2

T46

221

auto[1]

34472917

1

T1

8

T3

20372

T4

12

---

Summary for Variable cp_txempty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_txempty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1839481

1

T1

225

T4

11

T5

1

auto[1]

34605404

1

T1

122

T3

20372

T4

1

---

Summary for Variable cp_txfull

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_txfull

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

36444872

1

T1

347

T3

20372

T4

12

auto[1]

13

1

T170

2

T173

1

T311

1