Group : tb.dut.u_i2c_protocol_cov::i2c_protocol_cov_cg
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Group : tb.dut.u_i2c_protocol_cov::i2c_protocol_cov_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
91.30 91.30 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_sva_0.1/i2c_protocol_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
i2c_protocol_cov_cg 91.30 1 100 1 64 64



Group Instance : i2c_protocol_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
91.30 1 100 1 64 64



Summary for Group Instance i2c_protocol_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 47 6 41 87.23
Crosses 68 4 64 94.12


Variables for Group Instance i2c_protocol_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
RStart_before_read_data_ACK_cp 1 0 1 100.00 100 1 1 0
RStart_during_address_Ack_cp 1 0 1 100.00 100 1 1 0
RStart_during_address_transmission_cp 1 0 1 100.00 100 1 1 0
RStart_during_read_data_cp 1 0 1 100.00 100 1 1 0
RStart_during_rw_bit_cp 1 1 0 0.00 100 1 1 0
RStart_during_write_data_cp 1 0 1 100.00 100 1 1 0
Read_data_ack_before_stop_cp 1 1 0 0.00 100 1 1 0
Rstart_after_Address_Ack_cp 1 0 1 100.00 100 1 1 0
Rstart_after_Address_Nack_cp 1 0 1 100.00 100 1 1 0
Start_followed_by_Rstart_cp 1 0 1 100.00 100 1 1 2
Stop_after_read_data_Nack_cp 1 0 1 100.00 100 1 1 0
Stop_after_read_data_ack_cp 1 1 0 0.00 100 1 1 0
Stop_after_write_data_Nack_cp 1 0 1 100.00 100 1 1 0
Stop_after_write_data_ack_cp 1 0 1 100.00 100 1 1 0
Stop_without_ACK_after_addr_cp 1 1 0 0.00 100 1 1 0
Stop_without_ACK_after_data_cp 1 0 1 100.00 100 1 1 0
Stop_without_ACK_after_read_cp 1 1 0 0.00 100 1 1 0
Stop_without_ACK_after_write_cp 1 1 0 0.00 100 1 1 0
bus_state_cp 17 0 17 100.00 100 1 1 0
ip_mode_cp 2 0 2 100.00 100 1 1 0
num_rd_bytes_cp 5 0 5 100.00 100 1 1 0
num_wr_bytes_cp 5 0 5 100.00 100 1 1 0


Crosses for Group Instance i2c_protocol_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
bus_state_x_ip_mode_cp 34 1 33 97.06 100 1 1 0
num_rd_bytes_x_ip_mode_cp 10 0 10 100.00 100 1 1 0
num_wr_bytes_x_ip_mode_cp 10 0 10 100.00 100 1 1 0
Stop_after_write_data_ack_x_ip_mode_cp 2 0 2 100.00 100 1 1 0
Stop_after_read_data_ack_x_ip_mode_cp 2 2 0 0.00 100 1 1 0
Stop_after_write_data_Nack_x_ip_mode_cp 2 1 1 50.00 100 1 1 0
Stop_after_read_data_Nack_x_ip_mode_cp 2 0 2 100.00 100 1 1 0
Rstart_after_Address_Ack_x_ip_mode_cp 2 0 2 100.00 100 1 1 0
Rstart_after_Address_Nack_x_ip_mode_cp 2 0 2 100.00 100 1 1 0
Start_followed_by_Rstart_cp_x_ip_mode_cp 2 0 2 100.00 100 1 1 0


Summary for Variable RStart_before_read_data_ACK_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for RStart_before_read_data_ACK_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Start_before_read_data_ACK_Nack 13325 1 T1 23 T46 11 T57 17


Summary for Variable RStart_during_address_Ack_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for RStart_during_address_Ack_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
Start_during_address_Acknowledge 8 1 T51 4 T52 4


Summary for Variable RStart_during_address_transmission_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for RStart_during_address_transmission_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNT
Start_during_address_transmission 1 1 T280 1


Summary for Variable RStart_during_read_data_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for RStart_during_read_data_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
Start_during_read_data 24 1 T51 12 T52 12


Summary for Variable RStart_during_rw_bit_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 1 0 0.00


User Defined Bins for RStart_during_rw_bit_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
Start_during_rw_bit 0 1 1


Summary for Variable RStart_during_write_data_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for RStart_during_write_data_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Start_during_write_data 21923 1 T1 17 T7 8 T46 7


Summary for Variable Read_data_ack_before_stop_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 1 0 0.00


User Defined Bins for Read_data_ack_before_stop_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
Read_data_ack_before_stop 0 1 1


Summary for Variable Rstart_after_Address_Ack_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for Rstart_after_Address_Ack_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Rstart_after_Address_Ack 21 1 T12 1 T51 10 T52 10


Summary for Variable Rstart_after_Address_Nack_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for Rstart_after_Address_Nack_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Rstart_after_Address_Nack 69 1 T6 1 T20 1 T21 2


Summary for Variable Start_followed_by_Rstart_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for Start_followed_by_Rstart_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
unused 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 4 1 T281 1 T282 2 T280 1


Summary for Variable Stop_after_read_data_Nack_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for Stop_after_read_data_Nack_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Stop_after_read_data_Nack 11070 1 T1 9 T3 16 T6 2


Summary for Variable Stop_after_read_data_ack_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 1 0 0.00


User Defined Bins for Stop_after_read_data_ack_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
Stop_after_read_data_ack 0 1 1


Summary for Variable Stop_after_write_data_Nack_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for Stop_after_write_data_Nack_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Stop_after_write_data_Nack 55 1 T20 2 T21 1 T31 1


Summary for Variable Stop_after_write_data_ack_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for Stop_after_write_data_ack_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Stop_after_write_data_ack 9159 1 T1 6 T10 10 T46 4


Summary for Variable Stop_without_ACK_after_addr_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 1 0 0.00


User Defined Bins for Stop_without_ACK_after_addr_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
Stop_without_ACK_after_addr 0 1 1


Summary for Variable Stop_without_ACK_after_data_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for Stop_without_ACK_after_data_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Stop_without_ACK_after_data 6102 1 T1 6 T46 4 T55 2


Summary for Variable Stop_without_ACK_after_read_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 1 0 0.00


User Defined Bins for Stop_without_ACK_after_read_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
Stop_without_ACK_after_read 0 1 1


Summary for Variable Stop_without_ACK_after_write_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 1 0 0.00


User Defined Bins for Stop_without_ACK_after_write_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
Stop_without_ACK_after_write 0 1 1


Summary for Variable bus_state_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 17 0 17 100.00


User Defined Bins for bus_state_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
idle 242021 1 T1 1 T2 9 T3 1
stop 21187 1 T1 15 T2 2 T3 16
write_data_nack 26311 1 T53 4 T54 4 T20 1321
write_data_ack 1438167 1 T1 662 T7 368 T10 620
read_data_nack 91535 1 T1 105 T3 68 T4 4
read_data_ack 1154371 1 T1 781 T3 3787 T4 41
write_data 9858938 1 T1 4755 T7 2649 T9 3
read_data 8077173 1 T1 5337 T3 27040 T4 249
write_addr_nack 27304 1 T6 777 T20 219 T21 126
write_addr_ack 109565 1 T1 84 T7 30 T9 11
read_addr_nack 60130 1 T6 2218 T20 1050 T21 1808
read_addr_ack 88418 1 T1 110 T3 62 T4 3
write 130681 1 T1 96 T6 6 T7 36
read 76099 1 T1 96 T3 51 T4 3
addr 1223607 1 T1 1181 T3 290 T4 23
rstart 91856 1 T1 105 T6 2 T7 21
start 56619 1 T1 38 T3 41 T4 2


Summary for Variable ip_mode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for ip_mode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
device 12834907 1 T1 13366 T4 326 T5 914
host 9939075 1 T2 11 T3 31356 T6 4164


Summary for Variable num_rd_bytes_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 5 0 5 100.00


User Defined Bins for num_rd_bytes_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
sixtyfour 33986 1 T3 487 T8 363 T45 4
high 1235696 1 T3 9464 T8 7280 T46 48
mid 1938965 1 T1 245 T3 10530 T5 343
low 4667187 1 T1 4723 T3 9472 T4 249
one 513164 1 T1 599 T3 474 T4 24


Summary for Variable num_wr_bytes_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 5 0 5 100.00


User Defined Bins for num_wr_bytes_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
sixtyfour 39352 1 T55 54 T164 30 T44 26
high 1239057 1 T55 1118 T164 550 T47 35
mid 1966370 1 T1 768 T7 396 T10 1035
low 5149951 1 T1 3546 T7 2185 T10 2777
one 638323 1 T1 525 T7 212 T10 251


Summary for Cross bus_state_x_ip_mode_cp

Samples crossed: bus_state_cp ip_mode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 34 1 33 97.06 1


Automatically Generated Cross Bins for bus_state_x_ip_mode_cp

Uncovered bins
bus_state_cpip_mode_cpCOUNTAT LEASTNUMBERSTATUS
[read_addr_nack] [device] 0 1 1


Covered bins
bus_state_cpip_mode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
idle device 237333 1 T1 1 T4 1 T5 1
idle host 4688 1 T2 9 T3 1 T6 1
stop device 12223 1 T1 15 T46 10 T55 2
stop host 8964 1 T2 2 T3 16 T6 4
write_data_nack device 400 1 T53 4 T54 4 T56 4
write_data_nack host 25911 1 T20 1321 T21 1313 T275 25
write_data_ack device 845016 1 T1 662 T7 368 T46 427
write_data_ack host 593151 1 T10 620 T43 445 T44 292
read_data_nack device 64739 1 T1 105 T4 4 T5 4
read_data_nack host 26796 1 T3 68 T6 8 T8 52
read_data_ack device 500264 1 T1 781 T4 41 T5 121
read_data_ack host 654107 1 T3 3787 T6 123 T8 2905
write_data device 6301069 1 T1 4755 T7 2649 T46 3047
write_data host 3557869 1 T9 3 T10 3678 T43 2684
read_data device 3366087 1 T1 5337 T4 249 T5 754
read_data host 4711086 1 T3 27040 T6 895 T8 20707
write_addr_nack device 20 1 T51 4 T61 4 T62 4
write_addr_nack host 27284 1 T6 777 T20 219 T21 126
write_addr_ack device 95788 1 T1 84 T7 30 T46 41
write_addr_ack host 13777 1 T9 11 T10 41 T43 45
read_addr_nack host 60130 1 T6 2218 T20 1050 T21 1808
read_addr_ack device 68490 1 T1 110 T4 3 T5 4
read_addr_ack host 19928 1 T3 62 T6 6 T8 45
write device 114189 1 T1 96 T7 36 T46 48
write host 16492 1 T6 6 T9 17 T10 44
read device 58638 1 T1 96 T4 3 T5 3
read host 17461 1 T3 51 T6 10 T8 39
addr device 1047730 1 T1 1181 T4 23 T5 25
addr host 175877 1 T3 290 T6 102 T8 231
rstart device 90314 1 T1 105 T7 21 T46 36
rstart host 1542 1 T6 2 T19 6 T20 6
start device 32607 1 T1 38 T4 2 T5 2
start host 24012 1 T3 41 T6 12 T8 32


Summary for Cross num_rd_bytes_x_ip_mode_cp

Samples crossed: ip_mode_cp num_rd_bytes_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 10 0 10 100.00


Automatically Generated Cross Bins for num_rd_bytes_x_ip_mode_cp

Bins
ip_mode_cpnum_rd_bytes_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
device sixtyfour 1639 1 T74 76 T283 78 T284 72
device high 84672 1 T46 48 T73 461 T74 1864
device mid 384870 1 T1 245 T5 343 T46 843
device low 2618823 1 T1 4723 T4 249 T5 492
device one 365925 1 T1 599 T4 24 T5 24
host sixtyfour 32347 1 T3 487 T8 363 T45 4
host high 1151024 1 T3 9464 T8 7280 T45 543
host mid 1554095 1 T3 10530 T6 33 T8 7954
host low 2048364 1 T3 9472 T6 887 T8 7336
host one 147239 1 T3 474 T6 56 T8 364


Summary for Cross num_wr_bytes_x_ip_mode_cp

Samples crossed: ip_mode_cp num_wr_bytes_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 10 0 10 100.00


Automatically Generated Cross Bins for num_wr_bytes_x_ip_mode_cp

Bins
ip_mode_cpnum_wr_bytes_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
device sixtyfour 10752 1 T55 54 T164 30 T166 30
device high 315977 1 T55 1118 T164 550 T47 35
device mid 876299 1 T1 768 T7 396 T46 289
device low 3930949 1 T1 3546 T7 2185 T46 2596
device one 541353 1 T1 525 T7 212 T46 294
host sixtyfour 28600 1 T44 26 T19 318 T155 24
host high 923080 1 T44 490 T19 6326 T155 490
host mid 1090071 1 T10 1035 T43 106 T44 540
host low 1219002 1 T10 2777 T43 2443 T44 484
host one 96970 1 T10 251 T43 283 T44 26


Summary for Cross Stop_after_write_data_ack_x_ip_mode_cp

Samples crossed: Stop_after_write_data_ack_cp ip_mode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 2 0 2 100.00


Automatically Generated Cross Bins for Stop_after_write_data_ack_x_ip_mode_cp

Bins
Stop_after_write_data_ack_cpip_mode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Stop_after_write_data_ack device 6079 1 T1 6 T46 4 T55 2
Stop_after_write_data_ack host 3080 1 T10 10 T43 13 T19 9


Summary for Cross Stop_after_read_data_ack_x_ip_mode_cp

Samples crossed: Stop_after_read_data_ack_cp ip_mode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 2 2 0 0.00 2


Automatically Generated Cross Bins for Stop_after_read_data_ack_x_ip_mode_cp

Uncovered bins
Stop_after_read_data_ack_cpip_mode_cpCOUNTAT LEASTNUMBERSTATUS
* * -- -- 2


Summary for Cross Stop_after_write_data_Nack_x_ip_mode_cp

Samples crossed: Stop_after_write_data_Nack_cp ip_mode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 2 1 1 50.00 1


Automatically Generated Cross Bins for Stop_after_write_data_Nack_x_ip_mode_cp

Element holes
Stop_after_write_data_Nack_cpip_mode_cpCOUNTAT LEASTNUMBERSTATUS
* [device] 0 1 1


Covered bins
Stop_after_write_data_Nack_cpip_mode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Stop_after_write_data_Nack host 55 1 T20 2 T21 1 T31 1


Summary for Cross Stop_after_read_data_Nack_x_ip_mode_cp

Samples crossed: Stop_after_read_data_Nack_cp ip_mode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 2 0 2 100.00


Automatically Generated Cross Bins for Stop_after_read_data_Nack_x_ip_mode_cp

Bins
Stop_after_read_data_Nack_cpip_mode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Stop_after_read_data_Nack device 5781 1 T1 9 T46 6 T57 7
Stop_after_read_data_Nack host 5289 1 T3 16 T6 2 T8 12


Summary for Cross Rstart_after_Address_Ack_x_ip_mode_cp

Samples crossed: Rstart_after_Address_Ack_cp ip_mode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 2 0 2 100.00


Automatically Generated Cross Bins for Rstart_after_Address_Ack_x_ip_mode_cp

Bins
Rstart_after_Address_Ack_cpip_mode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
Rstart_after_Address_Ack device 20 1 T51 10 T52 10
Rstart_after_Address_Ack host 1 1 T12 1 - -


Summary for Cross Rstart_after_Address_Nack_x_ip_mode_cp

Samples crossed: Rstart_after_Address_Nack_cp ip_mode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 2 0 2 100.00


Automatically Generated Cross Bins for Rstart_after_Address_Nack_x_ip_mode_cp

Bins
Rstart_after_Address_Nack_cpip_mode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Rstart_after_Address_Nack device 8 1 T51 4 T52 4 - -
Rstart_after_Address_Nack host 61 1 T6 1 T20 1 T21 2


Summary for Cross Start_followed_by_Rstart_cp_x_ip_mode_cp

Samples crossed: Start_followed_by_Rstart_cp ip_mode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 2 0 2 100.00


Automatically Generated Cross Bins for Start_followed_by_Rstart_cp_x_ip_mode_cp

Excluded/Illegal bins
Start_followed_by_Rstart_cpip_mode_cpCOUNTSTATUS
[auto[0]] [device , host] -- Excluded (2 bins)


Covered bins
Start_followed_by_Rstart_cpip_mode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
auto[1] device 1 1 T280 1 - -
auto[1] host 3 1 T281 1 T282 2

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%