Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	31895490	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

8206970

1

T1

294

T2

15

T3

10306

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	39288398	1			T1	762		T2	18		T3	21463
values[0x0]	406003	1			T1	219		T2	8		T3	95
values[0x1]	408059	1			T1	173		T2	10		T3	86

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	22255142	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

17847318

1

T1

527

T2

19

T3

12661

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	146320	1			T1	4		T3	64		T6	502
valid_sources[0x01]	152898	1			T1	1		T3	83		T5	2
valid_sources[0x02]	159010	1			T1	5		T3	57		T7	3
valid_sources[0x03]	156779	1			T1	5		T3	53		T6	504
valid_sources[0x04]	155514	1			T1	1		T3	69		T8	87
valid_sources[0x05]	159248	1			T1	4		T3	105		T5	1
valid_sources[0x06]	151684	1			T1	8		T3	89		T6	1
valid_sources[0x07]	152053	1			T1	5		T3	69		T8	84
valid_sources[0x08]	152746	1			T1	2		T3	62		T8	114
valid_sources[0x09]	163840	1			T1	4		T3	107		T6	4
valid_sources[0x0a]	175566	1			T1	3		T3	87		T6	1
valid_sources[0x0b]	146961	1			T3	63		T6	2		T8	106
valid_sources[0x0c]	218296	1			T1	3		T3	79		T6	1
valid_sources[0x0d]	157647	1			T1	3		T3	97		T6	2
valid_sources[0x0e]	148772	1			T1	1		T3	116		T5	3
valid_sources[0x0f]	153429	1			T1	3		T3	77		T8	83
valid_sources[0x10]	155308	1			T1	8		T3	77		T7	6
valid_sources[0x11]	187530	1			T1	5		T3	118		T8	92
valid_sources[0x12]	157493	1			T1	3		T3	87		T6	11
valid_sources[0x13]	157629	1			T1	7		T3	107		T6	1
valid_sources[0x14]	167094	1			T1	1		T3	96		T6	2
valid_sources[0x15]	149219	1			T1	5		T3	100		T7	1
valid_sources[0x16]	151475	1			T1	2		T3	47		T6	1
valid_sources[0x17]	153180	1			T1	9		T3	70		T7	1
valid_sources[0x18]	154976	1			T1	4		T3	87		T8	109
valid_sources[0x19]	163314	1			T1	4		T3	90		T8	87
valid_sources[0x1a]	148852	1			T1	2		T3	86		T8	50
valid_sources[0x1b]	154164	1			T1	7		T2	1		T3	78
valid_sources[0x1c]	156051	1			T1	2		T3	56		T6	1
valid_sources[0x1d]	193885	1			T1	3		T2	1		T3	111
valid_sources[0x1e]	152925	1			T1	2		T3	71		T6	4
valid_sources[0x1f]	159693	1			T1	4		T3	77		T6	2
valid_sources[0x20]	151729	1			T1	4		T3	88		T6	2
valid_sources[0x21]	153806	1			T1	6		T3	94		T6	2
valid_sources[0x22]	150700	1			T1	6		T3	70		T8	64
valid_sources[0x23]	178898	1			T1	4		T3	89		T6	13
valid_sources[0x24]	152476	1			T1	2		T3	77		T8	97
valid_sources[0x25]	153454	1			T1	3		T3	79		T8	91
valid_sources[0x26]	163052	1			T1	12		T2	1		T3	119
valid_sources[0x27]	160963	1			T1	7		T2	2		T3	75
valid_sources[0x28]	154976	1			T1	1		T3	100		T8	60
valid_sources[0x29]	143551	1			T1	3		T3	54		T8	97
valid_sources[0x2a]	150783	1			T1	5		T3	94		T8	112
valid_sources[0x2b]	143980	1			T1	3		T3	110		T7	1
valid_sources[0x2c]	159736	1			T1	2		T3	57		T6	1
valid_sources[0x2d]	151534	1			T1	3		T2	1		T3	81
valid_sources[0x2e]	158624	1			T1	3		T2	1		T3	84
valid_sources[0x2f]	150598	1			T1	1		T3	111		T6	2
valid_sources[0x30]	150911	1			T1	2		T3	96		T5	1
valid_sources[0x31]	152512	1			T1	8		T3	92		T5	3
valid_sources[0x32]	157059	1			T1	3		T3	96		T6	1
valid_sources[0x33]	157444	1			T3	73		T5	1		T6	1
valid_sources[0x34]	160623	1			T1	3		T3	64		T6	5
valid_sources[0x35]	153051	1			T1	3		T3	107		T6	1
valid_sources[0x36]	148967	1			T1	5		T3	84		T5	3
valid_sources[0x37]	163943	1			T1	1		T3	49		T5	1
valid_sources[0x38]	142706	1			T1	2		T2	1		T3	83
valid_sources[0x39]	172011	1			T1	3		T3	77		T7	1
valid_sources[0x3a]	152044	1			T1	7		T3	116		T8	102
valid_sources[0x3b]	150981	1			T1	2		T3	106		T6	15
valid_sources[0x3c]	169965	1			T1	6		T3	82		T8	94
valid_sources[0x3d]	154023	1			T1	7		T3	62		T6	8
valid_sources[0x3e]	155734	1			T1	5		T3	81		T6	1
valid_sources[0x3f]	163894	1			T1	3		T3	82		T6	1
valid_sources[0x40]	149235	1			T1	8		T3	98		T6	5
valid_sources[0x41]	180366	1			T1	2		T3	126		T7	1
valid_sources[0x42]	153979	1			T1	8		T3	64		T7	3
valid_sources[0x43]	147824	1			T1	5		T3	83		T5	2
valid_sources[0x44]	157637	1			T1	5		T3	105		T8	108
valid_sources[0x45]	154749	1			T1	5		T3	92		T6	1
valid_sources[0x46]	149788	1			T1	6		T3	82		T6	1
valid_sources[0x47]	172760	1			T1	1		T3	101		T8	85
valid_sources[0x48]	147140	1			T1	6		T3	106		T6	1
valid_sources[0x49]	152542	1			T1	3		T3	111		T8	101
valid_sources[0x4a]	165023	1			T1	7		T3	81		T6	4
valid_sources[0x4b]	152881	1			T1	10		T3	80		T6	1
valid_sources[0x4c]	160641	1			T1	4		T3	73		T8	86
valid_sources[0x4d]	156548	1			T1	16		T3	87		T6	6
valid_sources[0x4e]	149362	1			T1	4		T3	103		T8	116
valid_sources[0x4f]	160330	1			T1	4		T3	77		T6	502
valid_sources[0x50]	145864	1			T1	1		T3	82		T5	1
valid_sources[0x51]	152929	1			T1	2		T3	95		T6	498
valid_sources[0x52]	144482	1			T1	7		T3	75		T6	2
valid_sources[0x53]	161412	1			T1	5		T3	40		T6	4
valid_sources[0x54]	153131	1			T1	4		T3	75		T5	2
valid_sources[0x55]	158722	1			T1	5		T3	44		T8	113
valid_sources[0x56]	158631	1			T1	7		T3	75		T6	1
valid_sources[0x57]	148965	1			T1	4		T3	60		T6	2
valid_sources[0x58]	148315	1			T1	3		T3	75		T8	147
valid_sources[0x59]	156064	1			T1	4		T3	90		T6	505
valid_sources[0x5a]	149681	1			T1	7		T3	70		T6	1
valid_sources[0x5b]	151717	1			T1	2		T3	55		T8	82
valid_sources[0x5c]	145324	1			T1	1		T3	99		T8	96
valid_sources[0x5d]	145483	1			T1	4		T3	74		T6	2
valid_sources[0x5e]	161187	1			T1	7		T2	1		T3	113
valid_sources[0x5f]	148601	1			T1	3		T3	110		T6	2
valid_sources[0x60]	159554	1			T1	9		T2	2		T3	100
valid_sources[0x61]	164070	1			T1	3		T3	77		T5	2
valid_sources[0x62]	153440	1			T1	5		T3	93		T8	81
valid_sources[0x63]	157317	1			T1	4		T3	99		T6	1
valid_sources[0x64]	177521	1			T1	4		T3	75		T7	2
valid_sources[0x65]	155396	1			T1	4		T3	42		T6	2
valid_sources[0x66]	167874	1			T1	7		T3	101		T6	498
valid_sources[0x67]	150645	1			T1	1		T2	2		T3	61
valid_sources[0x68]	157522	1			T1	11		T2	1		T3	54
valid_sources[0x69]	164469	1			T1	4		T3	109		T5	1
valid_sources[0x6a]	150632	1			T1	4		T3	98		T8	126
valid_sources[0x6b]	163046	1			T1	8		T3	83		T8	109
valid_sources[0x6c]	151723	1			T1	5		T3	107		T6	1
valid_sources[0x6d]	148001	1			T1	8		T2	1		T3	81
valid_sources[0x6e]	160521	1			T1	5		T3	68		T6	3
valid_sources[0x6f]	154076	1			T1	3		T2	1		T3	66
valid_sources[0x70]	155897	1			T1	12		T3	86		T6	1
valid_sources[0x71]	170303	1			T1	10		T3	53		T8	102
valid_sources[0x72]	160577	1			T1	6		T3	81		T6	1
valid_sources[0x73]	148512	1			T1	7		T3	101		T5	5
valid_sources[0x74]	147058	1			T1	1		T3	122		T6	1
valid_sources[0x75]	155940	1			T1	4		T2	1		T3	79
valid_sources[0x76]	163706	1			T1	4		T3	118		T6	1
valid_sources[0x77]	145248	1			T1	5		T3	102		T6	2
valid_sources[0x78]	159468	1			T1	3		T3	86		T6	9
valid_sources[0x79]	156419	1			T1	4		T3	89		T6	2
valid_sources[0x7a]	151047	1			T1	4		T3	69		T6	8
valid_sources[0x7b]	147543	1			T1	5		T3	108		T6	3
valid_sources[0x7c]	171989	1			T1	2		T3	104		T5	2
valid_sources[0x7d]	152542	1			T1	3		T3	90		T8	85
valid_sources[0x7e]	147426	1			T1	5		T3	75		T6	1
valid_sources[0x7f]	147541	1			T1	7		T3	93		T8	119
valid_sources[0x80]	163892	1			T1	8		T3	104		T6	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7846284

1

T1

151

T2

10

T3

10159

values[0x0]

all_enables

biggest_size

213591

1

T1

94

T2

4

T3

76

values[0x1]

all_enables

biggest_size

147095

1

T1

49

T2

1

T3

71