Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.48	100.00	100.00	93.91			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	396436424	0	0	0
ctrl_rd_A	396436424	1866	0	0
host_fifo_config_rd_A	396436424	4548	0	0
host_nack_handler_timeout_rd_A	396436424	1195	0	0
host_timeout_ctrl_rd_A	396436424	978	0	0
intr_enable_rd_A	396436424	4126	0	0
ovrd_rd_A	396436424	2557	0	0
target_fifo_config_rd_A	396436424	1043	0	0
target_id_rd_A	396436424	1645	0	0
target_timeout_ctrl_rd_A	396436424	1136	0	0
timeout_ctrl_rd_A	396436424	1452	0	0
timing0_rd_A	396436424	1274	0	0
timing1_rd_A	396436424	1238	0	0
timing2_rd_A	396436424	1151	0	0
timing3_rd_A	396436424	1097	0	0
timing4_rd_A	396436424	1300	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396436424	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396436424	1866	0	0
T101	6879	76	0	0
T102	7540	122	0	0
T103	3568	35	0	0
T104	2700	28	0	0
T105	3207	9	0	0
T106	6594	98	0	0
T107	6408	14	0	0
T108	4967	11	0	0
T109	6635	148	0	0
T110	45767	277	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396436424	4548	0	0
T83	509556	221	0	0
T111	0	139	0	0
T112	0	193	0	0
T113	0	150	0	0
T114	0	133	0	0
T115	0	147	0	0
T116	0	161	0	0
T117	0	463	0	0
T118	0	192	0	0
T119	0	139	0	0
T120	28273	0	0	0
T121	142387	0	0	0
T122	190011	0	0	0
T123	18562	0	0	0
T124	49267	0	0	0
T125	12429	0	0	0
T126	3408	0	0	0
T127	58047	0	0	0
T128	191645	0	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396436424	1195	0	0
T101	6879	42	0	0
T102	7540	49	0	0
T103	3568	9	0	0
T104	2700	6	0	0
T105	3207	2	0	0
T106	6594	123	0	0
T107	6408	18	0	0
T108	4967	75	0	0
T109	6635	53	0	0
T110	45767	217	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396436424	978	0	0
T101	6879	21	0	0
T102	7540	54	0	0
T103	3568	14	0	0
T104	2700	1	0	0
T105	3207	10	0	0
T106	6594	109	0	0
T107	6408	51	0	0
T108	4967	26	0	0
T109	6635	21	0	0
T110	45767	251	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396436424	4126	0	0
T51	152682	0	0	0
T101	0	148	0	0
T102	0	365	0	0
T103	0	22	0	0
T104	0	52	0	0
T105	0	4	0	0
T106	0	106	0	0
T107	0	66	0	0
T117	176980	8	0	0
T129	0	37	0	0
T130	0	13	0	0
T131	13531	0	0	0
T132	1799	0	0	0
T133	143234	0	0	0
T134	140921	0	0	0
T135	16830	0	0	0
T136	315104	0	0	0
T137	11163	0	0	0
T138	15787	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396436424	2557	0	0
T14	257139	0	0	0
T18	5957	0	0	0
T25	23554	0	0	0
T96	2856	44	0	0
T139	0	54	0	0
T140	0	35	0	0
T141	0	31	0	0
T142	0	56	0	0
T143	0	45	0	0
T144	0	83	0	0
T145	0	64	0	0
T146	0	44	0	0
T147	0	73	0	0
T148	50598	0	0	0
T149	104162	0	0	0
T150	41916	0	0	0
T151	93129	0	0	0
T152	17013	0	0	0
T153	10988	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396436424	1043	0	0
T101	6879	30	0	0
T102	7540	73	0	0
T103	3568	22	0	0
T104	2700	12	0	0
T105	3207	8	0	0
T106	6594	69	0	0
T107	6408	57	0	0
T108	4967	28	0	0
T109	6635	23	0	0
T110	45767	228	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396436424	1645	0	0
T101	6879	69	0	0
T102	7540	111	0	0
T103	3568	13	0	0
T104	2700	8	0	0
T105	3207	18	0	0
T106	6594	120	0	0
T107	6408	87	0	0
T108	4967	23	0	0
T109	6635	37	0	0
T110	45767	251	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396436424	1136	0	0
T101	6879	37	0	0
T102	7540	63	0	0
T103	3568	8	0	0
T105	3207	1	0	0
T106	6594	121	0	0
T107	6408	33	0	0
T108	4967	15	0	0
T109	6635	8	0	0
T110	45767	299	0	0
T154	7308	4	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396436424	1452	0	0
T101	6879	40	0	0
T102	7540	91	0	0
T103	3568	32	0	0
T104	2700	4	0	0
T105	3207	12	0	0
T106	6594	122	0	0
T107	6408	39	0	0
T108	4967	20	0	0
T109	6635	18	0	0
T110	45767	261	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396436424	1274	0	0
T101	6879	50	0	0
T102	7540	53	0	0
T103	3568	7	0	0
T104	2700	4	0	0
T105	3207	9	0	0
T106	6594	107	0	0
T107	6408	43	0	0
T108	4967	3	0	0
T109	6635	34	0	0
T110	45767	267	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396436424	1238	0	0
T101	6879	20	0	0
T102	7540	51	0	0
T103	3568	9	0	0
T104	2700	6	0	0
T105	3207	11	0	0
T106	6594	127	0	0
T107	6408	42	0	0
T108	4967	55	0	0
T109	6635	24	0	0
T110	45767	299	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396436424	1151	0	0
T101	6879	28	0	0
T102	7540	70	0	0
T103	3568	1	0	0
T105	3207	29	0	0
T106	6594	118	0	0
T107	6408	44	0	0
T108	4967	37	0	0
T109	6635	17	0	0
T110	45767	250	0	0
T154	7308	10	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396436424	1097	0	0
T101	6879	5	0	0
T102	7540	62	0	0
T103	3568	11	0	0
T104	2700	1	0	0
T105	3207	9	0	0
T106	6594	101	0	0
T107	6408	44	0	0
T108	4967	17	0	0
T109	6635	44	0	0
T110	45767	222	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396436424	1300	0	0
T101	6879	26	0	0
T102	7540	72	0	0
T103	3568	14	0	0
T104	2700	3	0	0
T105	3207	15	0	0
T106	6594	93	0	0
T107	6408	57	0	0
T108	4967	23	0	0
T109	6635	37	0	0
T110	45767	262	0	0