Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	27193073	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

7684343

1

T1

150

T2

292

T3

1291

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	34072516	1			T1	273		T2	716		T3	8350
values[0x0]	398888	1			T1	10		T2	177		T3	205
values[0x1]	406012	1			T1	7		T2	172		T3	212

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	18992884	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

15884532

1

T1

177

T2

519

T3

3600

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	137341	1			T1	1		T2	8		T3	19
valid_sources[0x01]	144752	1			T1	2		T2	12		T3	38
valid_sources[0x02]	149171	1			T2	3		T3	34		T5	109
valid_sources[0x03]	142480	1			T2	1		T3	29		T5	157
valid_sources[0x04]	137537	1			T1	4		T2	3		T3	37
valid_sources[0x05]	137107	1			T1	1		T2	3		T3	45
valid_sources[0x06]	143225	1			T2	8		T3	17		T5	147
valid_sources[0x07]	131524	1			T1	1		T2	4		T3	25
valid_sources[0x08]	118141	1			T2	1		T3	13		T5	144
valid_sources[0x09]	137858	1			T1	4		T2	3		T3	24
valid_sources[0x0a]	125887	1			T2	9		T3	29		T5	75
valid_sources[0x0b]	127448	1			T2	5		T3	39		T5	111
valid_sources[0x0c]	141643	1			T1	1		T2	7		T3	31
valid_sources[0x0d]	121945	1			T2	1		T3	60		T4	3
valid_sources[0x0e]	136948	1			T1	1		T2	3		T3	38
valid_sources[0x0f]	127218	1			T2	1		T3	27		T5	79
valid_sources[0x10]	132621	1			T3	59		T4	1		T5	125
valid_sources[0x11]	138312	1			T1	2		T2	4		T3	31
valid_sources[0x12]	144732	1			T2	10		T3	17		T5	236
valid_sources[0x13]	146385	1			T2	3		T3	19		T4	2
valid_sources[0x14]	144821	1			T1	1		T2	7		T3	31
valid_sources[0x15]	132286	1			T1	2		T2	7		T3	34
valid_sources[0x16]	143737	1			T2	4		T3	41		T5	116
valid_sources[0x17]	122688	1			T2	4		T3	35		T5	227
valid_sources[0x18]	159105	1			T1	1		T2	20		T3	25
valid_sources[0x19]	120471	1			T2	19		T3	23		T5	134
valid_sources[0x1a]	143493	1			T2	7		T3	12		T5	178
valid_sources[0x1b]	148722	1			T3	26		T5	123		T6	2
valid_sources[0x1c]	133475	1			T1	2		T2	1		T3	30
valid_sources[0x1d]	137264	1			T1	1		T2	11		T3	39
valid_sources[0x1e]	133151	1			T1	6		T3	67		T5	162
valid_sources[0x1f]	135607	1			T1	2		T2	2		T3	18
valid_sources[0x20]	142080	1			T1	1		T2	10		T3	34
valid_sources[0x21]	129156	1			T1	1		T3	27		T5	181
valid_sources[0x22]	145440	1			T2	3		T3	22		T4	5
valid_sources[0x23]	125363	1			T1	1		T2	12		T3	59
valid_sources[0x24]	127933	1			T2	8		T3	52		T5	163
valid_sources[0x25]	164118	1			T3	44		T5	168		T6	3
valid_sources[0x26]	120861	1			T2	11		T3	46		T5	165
valid_sources[0x27]	135904	1			T1	4		T3	24		T5	191
valid_sources[0x28]	143018	1			T2	4		T3	38		T5	115
valid_sources[0x29]	136133	1			T1	1		T2	2		T3	29
valid_sources[0x2a]	144854	1			T1	1		T2	1		T3	30
valid_sources[0x2b]	125893	1			T2	16		T3	31		T4	7
valid_sources[0x2c]	135652	1			T2	4		T3	32		T5	126
valid_sources[0x2d]	160138	1			T1	1		T2	3		T3	40
valid_sources[0x2e]	147083	1			T1	1		T2	9		T3	25
valid_sources[0x2f]	132310	1			T1	1		T2	3		T3	26
valid_sources[0x30]	131887	1			T1	1		T3	29		T5	173
valid_sources[0x31]	123089	1			T1	6		T2	5		T3	32
valid_sources[0x32]	121726	1			T3	11		T5	172		T6	9
valid_sources[0x33]	132143	1			T2	1		T3	45		T5	234
valid_sources[0x34]	133212	1			T2	5		T3	32		T5	114
valid_sources[0x35]	142577	1			T1	5		T3	27		T5	93
valid_sources[0x36]	157931	1			T3	47		T5	160		T6	1
valid_sources[0x37]	135484	1			T1	3		T3	48		T5	148
valid_sources[0x38]	139756	1			T2	1		T3	26		T5	86
valid_sources[0x39]	127255	1			T1	1		T2	1		T3	32
valid_sources[0x3a]	137963	1			T1	1		T2	14		T3	30
valid_sources[0x3b]	154974	1			T1	3		T2	2		T3	41
valid_sources[0x3c]	118235	1			T1	4		T3	22		T5	121
valid_sources[0x3d]	232096	1			T1	1		T3	29		T5	183
valid_sources[0x3e]	134677	1			T2	4		T3	29		T4	3
valid_sources[0x3f]	137889	1			T1	2		T3	23		T5	129
valid_sources[0x40]	129264	1			T1	3		T2	2		T3	13
valid_sources[0x41]	158562	1			T1	2		T2	6		T3	54
valid_sources[0x42]	133763	1			T1	2		T2	14		T3	17
valid_sources[0x43]	128113	1			T1	1		T2	12		T3	33
valid_sources[0x44]	128920	1			T1	1		T2	4		T3	55
valid_sources[0x45]	117999	1			T1	2		T2	3		T3	62
valid_sources[0x46]	120013	1			T1	1		T3	34		T5	157
valid_sources[0x47]	147423	1			T1	1		T2	4		T3	32
valid_sources[0x48]	134481	1			T3	18		T4	1		T5	130
valid_sources[0x49]	129061	1			T1	2		T2	5		T3	50
valid_sources[0x4a]	132724	1			T2	3		T3	57		T5	88
valid_sources[0x4b]	138202	1			T1	3		T2	5		T3	19
valid_sources[0x4c]	144036	1			T2	5		T3	57		T4	2
valid_sources[0x4d]	132673	1			T1	1		T2	3		T3	19
valid_sources[0x4e]	127996	1			T1	1		T2	24		T3	23
valid_sources[0x4f]	154290	1			T2	8		T3	44		T4	1
valid_sources[0x50]	130142	1			T2	2		T3	22		T5	143
valid_sources[0x51]	141613	1			T3	34		T5	120		T6	13
valid_sources[0x52]	122466	1			T2	2		T3	19		T5	163
valid_sources[0x53]	131803	1			T1	2		T2	5		T3	41
valid_sources[0x54]	144816	1			T2	11		T3	37		T5	174
valid_sources[0x55]	123028	1			T1	1		T2	2		T3	38
valid_sources[0x56]	133720	1			T1	2		T2	2		T3	25
valid_sources[0x57]	137948	1			T1	1		T2	2		T3	66
valid_sources[0x58]	131641	1			T1	2		T2	4		T3	34
valid_sources[0x59]	149189	1			T2	6		T3	40		T5	201
valid_sources[0x5a]	149421	1			T1	1		T2	6		T3	41
valid_sources[0x5b]	140125	1			T1	1		T2	4		T3	28
valid_sources[0x5c]	139294	1			T2	3		T3	25		T5	148
valid_sources[0x5d]	125667	1			T2	1		T3	44		T5	123
valid_sources[0x5e]	131223	1			T1	2		T3	33		T4	1
valid_sources[0x5f]	129605	1			T2	11		T3	37		T5	119
valid_sources[0x60]	135675	1			T2	4		T3	25		T5	137
valid_sources[0x61]	119425	1			T1	1		T2	8		T3	49
valid_sources[0x62]	133508	1			T3	38		T5	172		T6	4
valid_sources[0x63]	114999	1			T2	8		T3	54		T5	199
valid_sources[0x64]	133174	1			T1	2		T2	10		T3	24
valid_sources[0x65]	130974	1			T1	1		T3	25		T5	151
valid_sources[0x66]	123130	1			T1	1		T2	4		T3	32
valid_sources[0x67]	127599	1			T1	1		T2	4		T3	42
valid_sources[0x68]	127988	1			T1	2		T2	5		T3	16
valid_sources[0x69]	137573	1			T2	1		T3	49		T5	121
valid_sources[0x6a]	123083	1			T1	5		T2	7		T3	65
valid_sources[0x6b]	135919	1			T2	4		T3	27		T5	157
valid_sources[0x6c]	133806	1			T2	2		T3	36		T4	1
valid_sources[0x6d]	140104	1			T1	2		T3	32		T5	140
valid_sources[0x6e]	141837	1			T2	8		T3	19		T4	2
valid_sources[0x6f]	136189	1			T1	1		T2	4		T3	40
valid_sources[0x70]	118533	1			T1	2		T2	4		T3	29
valid_sources[0x71]	129362	1			T1	2		T2	5		T3	47
valid_sources[0x72]	135764	1			T1	1		T2	16		T3	48
valid_sources[0x73]	128339	1			T1	1		T2	8		T3	43
valid_sources[0x74]	133650	1			T1	1		T3	13		T5	88
valid_sources[0x75]	125961	1			T3	38		T5	94		T6	125
valid_sources[0x76]	141119	1			T1	2		T2	6		T3	39
valid_sources[0x77]	137389	1			T1	3		T2	17		T3	52
valid_sources[0x78]	121154	1			T3	40		T5	144		T6	3
valid_sources[0x79]	116400	1			T1	3		T2	2		T3	34
valid_sources[0x7a]	144932	1			T1	1		T3	36		T5	218
valid_sources[0x7b]	142092	1			T1	2		T2	2		T3	40
valid_sources[0x7c]	149262	1			T1	5		T2	11		T3	47
valid_sources[0x7d]	129775	1			T3	49		T5	178		T6	3
valid_sources[0x7e]	131884	1			T1	1		T2	5		T3	11
valid_sources[0x7f]	132658	1			T2	5		T3	31		T5	107
valid_sources[0x80]	128628	1			T2	18		T3	40		T5	117

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7306216

1

T1

136

T2

155

T3

1018

values[0x0]

all_enables

biggest_size

219915

1

T1

9

T2

91

T3

138

values[0x1]

all_enables

biggest_size

158212

1

T1

5

T2

46

T3

135