Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.48	100.00	100.00	93.91			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	382638397	0	0	0
ctrl_rd_A	382638397	2206	0	0
host_fifo_config_rd_A	382638397	2979	0	0
host_nack_handler_timeout_rd_A	382638397	1353	0	0
host_timeout_ctrl_rd_A	382638397	1221	0	0
intr_enable_rd_A	382638397	3987	0	0
ovrd_rd_A	382638397	2647	0	0
target_fifo_config_rd_A	382638397	1359	0	0
target_id_rd_A	382638397	1620	0	0
target_timeout_ctrl_rd_A	382638397	1331	0	0
timeout_ctrl_rd_A	382638397	1519	0	0
timing0_rd_A	382638397	1317	0	0
timing1_rd_A	382638397	1241	0	0
timing2_rd_A	382638397	1457	0	0
timing3_rd_A	382638397	1349	0	0
timing4_rd_A	382638397	1398	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382638397	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382638397	2206	0	0
T98	3525	35	0	0
T99	3456	31	0	0
T100	2498	38	0	0
T101	7354	3	0	0
T102	3064	83	0	0
T103	3009	45	0	0
T104	2314	35	0	0
T105	5538	11	0	0
T106	5936	51	0	0
T107	7586	157	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382638397	2979	0	0
T19	35801	0	0	0
T61	91409	0	0	0
T108	564790	221	0	0
T109	0	196	0	0
T110	0	210	0	0
T111	0	143	0	0
T112	0	78	0	0
T113	0	82	0	0
T114	0	143	0	0
T115	0	149	0	0
T116	0	189	0	0
T117	0	192	0	0
T118	7994	0	0	0
T119	13148	0	0	0
T120	56851	0	0	0
T121	14736	0	0	0
T122	81154	0	0	0
T123	495453	0	0	0
T124	47296	0	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382638397	1353	0	0
T98	3525	20	0	0
T99	3456	32	0	0
T100	2498	12	0	0
T101	7354	4	0	0
T102	3064	20	0	0
T103	3009	29	0	0
T104	2314	6	0	0
T106	5936	45	0	0
T107	7586	62	0	0
T125	1742	17	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382638397	1221	0	0
T98	3525	24	0	0
T99	3456	7	0	0
T100	2498	5	0	0
T101	7354	17	0	0
T102	3064	28	0	0
T103	3009	15	0	0
T104	2314	10	0	0
T106	5936	41	0	0
T107	7586	39	0	0
T126	1277	4	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382638397	3987	0	0
T98	0	3	0	0
T99	0	36	0	0
T100	0	66	0	0
T101	0	10	0	0
T102	0	74	0	0
T103	0	88	0	0
T104	0	55	0	0
T127	842261	9	0	0
T128	0	15	0	0
T129	0	6	0	0
T130	116666	0	0	0
T131	39438	0	0	0
T132	54327	0	0	0
T133	79594	0	0	0
T134	1418	0	0	0
T135	120873	0	0	0
T136	309959	0	0	0
T137	17399	0	0	0
T138	22848	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382638397	2647	0	0
T66	542506	0	0	0
T69	56037	0	0	0
T81	1161	27	0	0
T139	0	48	0	0
T140	0	51	0	0
T141	0	29	0	0
T142	0	29	0	0
T143	0	55	0	0
T144	0	64	0	0
T145	0	40	0	0
T146	0	39	0	0
T147	0	39	0	0
T148	51989	0	0	0
T149	67931	0	0	0
T150	49424	0	0	0
T151	117785	0	0	0
T152	39169	0	0	0
T153	50239	0	0	0
T154	268146	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382638397	1359	0	0
T98	3525	20	0	0
T99	3456	9	0	0
T100	2498	7	0	0
T102	3064	23	0	0
T103	3009	22	0	0
T104	2314	6	0	0
T105	5538	8	0	0
T106	5936	65	0	0
T107	7586	56	0	0
T126	1277	3	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382638397	1620	0	0
T98	3525	22	0	0
T99	3456	17	0	0
T100	2498	17	0	0
T101	7354	1	0	0
T102	3064	14	0	0
T103	3009	15	0	0
T104	2314	18	0	0
T105	5538	3	0	0
T106	5936	73	0	0
T107	7586	74	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382638397	1331	0	0
T98	3525	15	0	0
T99	3456	39	0	0
T100	2498	10	0	0
T101	7354	5	0	0
T102	3064	9	0	0
T103	3009	30	0	0
T104	2314	10	0	0
T105	5538	11	0	0
T106	5936	54	0	0
T107	7586	58	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382638397	1519	0	0
T98	3525	7	0	0
T99	3456	19	0	0
T100	2498	1	0	0
T101	7354	3	0	0
T102	3064	35	0	0
T103	3009	30	0	0
T104	2314	10	0	0
T105	5538	4	0	0
T106	5936	22	0	0
T107	7586	103	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382638397	1317	0	0
T98	3525	18	0	0
T99	3456	35	0	0
T100	2498	1	0	0
T101	7354	3	0	0
T102	3064	23	0	0
T103	3009	8	0	0
T104	2314	12	0	0
T105	5538	3	0	0
T106	5936	41	0	0
T107	7586	65	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382638397	1241	0	0
T98	3525	35	0	0
T100	2498	3	0	0
T101	7354	8	0	0
T102	3064	17	0	0
T103	3009	15	0	0
T104	2314	10	0	0
T105	5538	21	0	0
T106	5936	19	0	0
T107	7586	50	0	0
T125	1742	20	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382638397	1457	0	0
T98	3525	23	0	0
T99	3456	34	0	0
T100	2498	3	0	0
T101	7354	12	0	0
T102	3064	26	0	0
T103	3009	17	0	0
T104	2314	9	0	0
T105	5538	9	0	0
T106	5936	65	0	0
T107	7586	72	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382638397	1349	0	0
T98	3525	25	0	0
T99	3456	2	0	0
T100	2498	21	0	0
T101	7354	2	0	0
T102	3064	26	0	0
T103	3009	17	0	0
T104	2314	9	0	0
T105	5538	6	0	0
T106	5936	40	0	0
T107	7586	47	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382638397	1398	0	0
T98	3525	9	0	0
T99	3456	45	0	0
T100	2498	12	0	0
T101	7354	10	0	0
T102	3064	31	0	0
T103	3009	22	0	0
T104	2314	12	0	0
T105	5538	8	0	0
T106	5936	93	0	0
T107	7586	47	0	0