Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	25227729	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

6950766

1

T1

5869

T2

165

T3

146

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	31362306	1			T1	19610		T2	554		T3	645
values[0x0]	408001	1			T1	435		T2	40		T3	90
values[0x1]	408188	1			T1	424		T2	50		T3	118

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	17636434	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

14542061

1

T1

10023

T2

298

T3

375

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	126524	1			T1	90		T6	4		T8	12
valid_sources[0x01]	125564	1			T1	91		T5	2		T6	3
valid_sources[0x02]	139416	1			T1	68		T5	1		T6	4
valid_sources[0x03]	132409	1			T1	75		T5	4		T6	4
valid_sources[0x04]	121387	1			T1	93		T5	3		T6	3
valid_sources[0x05]	124867	1			T1	75		T6	4		T8	20
valid_sources[0x06]	116397	1			T1	81		T5	5		T6	10
valid_sources[0x07]	130132	1			T1	76		T5	4		T6	1
valid_sources[0x08]	135429	1			T1	77		T5	6		T6	1
valid_sources[0x09]	118305	1			T1	91		T5	3		T6	1
valid_sources[0x0a]	119012	1			T1	90		T5	3		T6	2
valid_sources[0x0b]	122986	1			T1	73		T5	3		T6	1
valid_sources[0x0c]	122600	1			T1	86		T5	1		T6	2
valid_sources[0x0d]	122934	1			T1	70		T5	2		T8	12
valid_sources[0x0e]	116968	1			T1	62		T5	3		T6	9
valid_sources[0x0f]	122838	1			T1	87		T2	1		T4	4
valid_sources[0x10]	118658	1			T1	64		T5	1		T6	4
valid_sources[0x11]	130405	1			T1	125		T5	6		T6	4
valid_sources[0x12]	116365	1			T1	61		T5	2		T6	5
valid_sources[0x13]	134731	1			T1	86		T5	3		T6	2
valid_sources[0x14]	121004	1			T1	68		T5	2		T6	3
valid_sources[0x15]	111252	1			T1	101		T5	3		T6	2
valid_sources[0x16]	137828	1			T1	77		T5	2		T6	2
valid_sources[0x17]	128782	1			T1	79		T5	5		T6	1
valid_sources[0x18]	127316	1			T1	63		T6	2		T7	1
valid_sources[0x19]	141507	1			T1	64		T5	2		T6	6
valid_sources[0x1a]	124560	1			T1	132		T2	1		T5	3
valid_sources[0x1b]	138542	1			T1	82		T4	1		T5	2
valid_sources[0x1c]	120817	1			T1	71		T5	1		T6	3
valid_sources[0x1d]	130859	1			T1	80		T5	2		T6	4
valid_sources[0x1e]	147027	1			T1	82		T2	14		T5	6
valid_sources[0x1f]	115965	1			T1	67		T5	1		T6	8
valid_sources[0x20]	127561	1			T1	92		T3	601		T5	2
valid_sources[0x21]	111920	1			T1	88		T6	4		T8	19
valid_sources[0x22]	125727	1			T1	70		T5	8		T6	5
valid_sources[0x23]	114947	1			T1	61		T5	2		T6	9
valid_sources[0x24]	145619	1			T1	72		T5	1		T6	4
valid_sources[0x25]	133462	1			T1	84		T5	4		T6	2
valid_sources[0x26]	118415	1			T1	78		T5	1		T6	2
valid_sources[0x27]	123065	1			T1	75		T5	1		T6	7
valid_sources[0x28]	128424	1			T1	66		T5	3		T8	16
valid_sources[0x29]	128455	1			T1	83		T5	1		T6	4
valid_sources[0x2a]	121305	1			T1	71		T5	1		T6	3
valid_sources[0x2b]	118922	1			T1	89		T5	1		T6	2
valid_sources[0x2c]	125849	1			T1	86		T6	4		T7	1
valid_sources[0x2d]	129558	1			T1	95		T5	3		T6	4
valid_sources[0x2e]	120577	1			T1	79		T4	1		T5	4
valid_sources[0x2f]	121720	1			T1	88		T5	4		T6	5
valid_sources[0x30]	108692	1			T1	103		T3	252		T5	1
valid_sources[0x31]	123077	1			T1	90		T4	1		T5	2
valid_sources[0x32]	122367	1			T1	66		T5	4		T6	3
valid_sources[0x33]	136030	1			T1	73		T5	2		T6	4
valid_sources[0x34]	116988	1			T1	87		T5	1		T6	5
valid_sources[0x35]	125976	1			T1	82		T5	3		T6	4
valid_sources[0x36]	131820	1			T1	96		T5	8		T6	3
valid_sources[0x37]	129898	1			T1	85		T5	6		T6	2
valid_sources[0x38]	132914	1			T1	60		T5	3		T6	3
valid_sources[0x39]	126724	1			T1	88		T2	1		T5	1
valid_sources[0x3a]	118453	1			T1	114		T5	8		T6	4
valid_sources[0x3b]	123272	1			T1	95		T5	1		T6	2
valid_sources[0x3c]	109685	1			T1	102		T5	6		T6	2
valid_sources[0x3d]	117786	1			T1	94		T5	3		T6	6
valid_sources[0x3e]	123443	1			T1	86		T6	3		T8	19
valid_sources[0x3f]	126788	1			T1	81		T5	2		T6	5
valid_sources[0x40]	113825	1			T1	61		T2	1		T5	3
valid_sources[0x41]	110520	1			T1	101		T5	2		T6	6
valid_sources[0x42]	130285	1			T1	106		T2	1		T5	2
valid_sources[0x43]	119348	1			T1	88		T6	4		T8	25
valid_sources[0x44]	129439	1			T1	92		T4	1		T5	3
valid_sources[0x45]	118197	1			T1	80		T2	1		T4	1
valid_sources[0x46]	125482	1			T1	37		T5	3		T6	2
valid_sources[0x47]	120717	1			T1	95		T5	4		T6	5
valid_sources[0x48]	145210	1			T1	78		T5	3		T6	4
valid_sources[0x49]	128379	1			T1	85		T5	2		T6	8
valid_sources[0x4a]	116205	1			T1	55		T5	3		T6	1
valid_sources[0x4b]	122424	1			T1	72		T5	2		T6	9
valid_sources[0x4c]	135887	1			T1	67		T5	6		T6	2
valid_sources[0x4d]	135608	1			T1	95		T5	2		T6	9
valid_sources[0x4e]	209880	1			T1	75		T5	3		T6	3
valid_sources[0x4f]	110336	1			T1	89		T5	1		T6	3
valid_sources[0x50]	120622	1			T1	89		T5	5		T6	5
valid_sources[0x51]	142913	1			T1	69		T4	3		T6	2
valid_sources[0x52]	137855	1			T1	61		T5	2		T6	2
valid_sources[0x53]	120059	1			T1	77		T5	3		T6	6
valid_sources[0x54]	131753	1			T1	87		T6	2		T7	4
valid_sources[0x55]	120860	1			T1	82		T5	2		T6	3
valid_sources[0x56]	117244	1			T1	78		T5	1		T6	5
valid_sources[0x57]	109006	1			T1	88		T2	137		T6	3
valid_sources[0x58]	115626	1			T1	72		T6	4		T8	17
valid_sources[0x59]	132791	1			T1	93		T5	10		T6	5
valid_sources[0x5a]	116694	1			T1	101		T5	3		T6	4
valid_sources[0x5b]	115086	1			T1	84		T5	1		T6	5
valid_sources[0x5c]	116359	1			T1	102		T2	2		T5	1
valid_sources[0x5d]	123773	1			T1	77		T8	17		T60	3
valid_sources[0x5e]	120213	1			T1	104		T6	4		T8	13
valid_sources[0x5f]	121346	1			T1	97		T5	2		T6	7
valid_sources[0x60]	131608	1			T1	79		T2	1		T5	2
valid_sources[0x61]	115582	1			T1	62		T5	2		T6	5
valid_sources[0x62]	144909	1			T1	85		T6	2		T8	14
valid_sources[0x63]	117405	1			T1	83		T2	1		T5	5
valid_sources[0x64]	126640	1			T1	69		T5	3		T6	2
valid_sources[0x65]	133692	1			T1	72		T5	5		T6	6
valid_sources[0x66]	134032	1			T1	96		T6	5		T8	11
valid_sources[0x67]	126603	1			T1	55		T4	1		T5	2
valid_sources[0x68]	117878	1			T1	102		T4	1		T6	6
valid_sources[0x69]	156078	1			T1	71		T4	1		T5	2
valid_sources[0x6a]	109029	1			T1	81		T6	2		T8	15
valid_sources[0x6b]	118209	1			T1	67		T6	3		T8	14
valid_sources[0x6c]	134383	1			T1	85		T5	3		T6	1
valid_sources[0x6d]	121662	1			T1	64		T5	3		T6	4
valid_sources[0x6e]	114106	1			T1	90		T5	6		T6	3
valid_sources[0x6f]	114669	1			T1	59		T5	3		T6	1
valid_sources[0x70]	130701	1			T1	64		T4	1		T5	1
valid_sources[0x71]	127185	1			T1	80		T2	1		T5	2
valid_sources[0x72]	115878	1			T1	75		T5	3		T6	3
valid_sources[0x73]	123310	1			T1	69		T5	6		T6	3
valid_sources[0x74]	126539	1			T1	130		T5	3		T6	8
valid_sources[0x75]	108162	1			T1	74		T4	1		T5	4
valid_sources[0x76]	130281	1			T1	58		T6	2		T8	19
valid_sources[0x77]	141124	1			T1	70		T5	7		T6	4
valid_sources[0x78]	126579	1			T1	82		T6	3		T7	1
valid_sources[0x79]	144546	1			T1	81		T4	1		T5	3
valid_sources[0x7a]	108306	1			T1	59		T5	4		T6	2
valid_sources[0x7b]	149858	1			T1	68		T6	4		T8	16
valid_sources[0x7c]	119609	1			T1	79		T5	2		T6	3
valid_sources[0x7d]	131551	1			T1	63		T5	4		T6	2
valid_sources[0x7e]	125390	1			T1	92		T5	1		T6	4
valid_sources[0x7f]	112348	1			T1	82		T5	1		T6	5
valid_sources[0x80]	124886	1			T1	79		T5	2		T6	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

6587333

1

T1

5324

T2

104

T3

90

values[0x0]

all_enables

biggest_size

215399

1

T1

293

T2

30

T3

33

values[0x1]

all_enables

biggest_size

148034

1

T1

252

T2

31

T3

23