Module Definition
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Module : i2c_fifos
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.00 100.00 100.00 40.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifos.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.i2c_core.u_fifos 80.00 100.00 100.00 40.00



Module Instance : tb.dut.i2c_core.u_fifos

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.00 100.00 100.00 40.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 99.86 83.33 98.32 93.48


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.58 97.74 79.23 93.33 100.00 i2c_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_acq_fifo_sram_adapter 95.85 100.00 84.91 98.51 100.00
u_fmt_fifo_sram_adapter 95.54 100.00 83.65 98.51 100.00
u_ram_1p 99.02 97.06 100.00 100.00
u_ram_arbiter 90.93 100.00 82.46 100.00 81.25
u_rx_fifo_sram_adapter 94.69 100.00 81.76 97.01 100.00
u_tx_fifo_sram_adapter 95.54 100.00 83.65 98.51 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : i2c_fifos
Line No.TotalCoveredPercent
TOTAL3131100.00
CONT_ASSIGN11411100.00
CONT_ASSIGN11511100.00
CONT_ASSIGN14711100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN18211100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18511100.00
CONT_ASSIGN21711100.00
CONT_ASSIGN21811100.00
CONT_ASSIGN22011100.00
CONT_ASSIGN25411100.00
CONT_ASSIGN25511100.00
CONT_ASSIGN25611100.00
CONT_ASSIGN25711100.00
CONT_ASSIGN25811100.00
CONT_ASSIGN25911100.00
CONT_ASSIGN26011100.00
CONT_ASSIGN26111100.00
CONT_ASSIGN26211100.00
CONT_ASSIGN26311100.00
CONT_ASSIGN26411100.00
CONT_ASSIGN26511100.00
ALWAYS27033100.00
CONT_ASSIGN27611100.00
CONT_ASSIGN27711100.00
CONT_ASSIGN27811100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN30411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifos.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifos.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
114 1 1
115 1 1
147 1 1
148 1 1
150 1 1
182 1 1
183 1 1
185 1 1
217 1 1
218 1 1
220 1 1
254 1 1
255 1 1
256 1 1
257 1 1
258 1 1
259 1 1
260 1 1
261 1 1
262 1 1
263 1 1
264 1 1
265 1 1
270 1 1
271 1 1
273 1 1
276 1 1
277 1 1
278 1 1
279 1 1
304 1 1


Branch Coverage for Module : i2c_fifos
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 270 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifos.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifos.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 270 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : i2c_fifos
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 2 40.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 2 40.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AcqWriteStableBeforeHandshake_A 393906982 0 0 0
FmtWriteStableBeforeHandshake_A 396360503 0 0 0
RamDepthSuffices_A 1678 1678 0 0
RamWidthSuffices_A 1678 1678 0 0
TxWriteStableBeforeHandshake_A 396360503 0 0 0


AcqWriteStableBeforeHandshake_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393906982 0 0 0

FmtWriteStableBeforeHandshake_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 396360503 0 0 0

RamDepthSuffices_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1678 1678 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

RamWidthSuffices_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1678 1678 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

TxWriteStableBeforeHandshake_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 396360503 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%