Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.48	100.00	100.00	93.91			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	397037409	0	0	0
ctrl_rd_A	397037409	2804	0	0
host_fifo_config_rd_A	397037409	4992	0	0
host_nack_handler_timeout_rd_A	397037409	1844	0	0
host_timeout_ctrl_rd_A	397037409	1856	0	0
intr_enable_rd_A	397037409	4597	0	0
ovrd_rd_A	397037409	2544	0	0
target_fifo_config_rd_A	397037409	2000	0	0
target_id_rd_A	397037409	2409	0	0
target_timeout_ctrl_rd_A	397037409	1888	0	0
timeout_ctrl_rd_A	397037409	2024	0	0
timing0_rd_A	397037409	1845	0	0
timing1_rd_A	397037409	1798	0	0
timing2_rd_A	397037409	1914	0	0
timing3_rd_A	397037409	1917	0	0
timing4_rd_A	397037409	1992	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397037409	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397037409	2804	0	0
T101	2894	29	0	0
T102	1908	5	0	0
T103	11163	218	0	0
T104	6277	25	0	0
T105	2100	38	0	0
T106	2893	3	0	0
T107	2524	5	0	0
T108	4599	51	0	0
T109	2604	30	0	0
T110	3773	41	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397037409	4992	0	0
T25	0	52	0	0
T31	530544	0	0	0
T57	52154	0	0	0
T111	334937	136	0	0
T112	0	83	0	0
T113	0	74	0	0
T114	0	74	0	0
T115	0	142	0	0
T116	0	124	0	0
T117	0	149	0	0
T118	0	73	0	0
T119	0	113	0	0
T120	22665	0	0	0
T121	396168	0	0	0
T122	45322	0	0	0
T123	121871	0	0	0
T124	14951	0	0	0
T125	72476	0	0	0
T126	906060	0	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397037409	1844	0	0
T101	2894	28	0	0
T102	1908	7	0	0
T103	11163	196	0	0
T104	6277	2	0	0
T105	2100	12	0	0
T106	2893	16	0	0
T107	2524	8	0	0
T108	4599	28	0	0
T109	2604	9	0	0
T110	3773	19	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397037409	1856	0	0
T101	2894	12	0	0
T102	1908	10	0	0
T103	11163	195	0	0
T104	6277	22	0	0
T105	2100	11	0	0
T106	2893	4	0	0
T108	4599	10	0	0
T109	2604	7	0	0
T110	3773	9	0	0
T127	2492	6	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397037409	4597	0	0
T25	539575	2	0	0
T101	0	61	0	0
T102	0	6	0	0
T103	0	189	0	0
T104	0	27	0	0
T128	0	12	0	0
T129	0	10	0	0
T130	0	11	0	0
T131	0	43	0	0
T132	0	10	0	0
T133	9978	0	0	0
T134	4487	0	0	0
T135	57624	0	0	0
T136	836813	0	0	0
T137	152846	0	0	0
T138	14994	0	0	0
T139	51347	0	0	0
T140	26387	0	0	0
T141	259019	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397037409	2544	0	0
T142	1886	36	0	0
T143	0	38	0	0
T144	0	31	0	0
T145	0	32	0	0
T146	0	27	0	0
T147	0	39	0	0
T148	0	45	0	0
T149	0	61	0	0
T150	0	71	0	0
T151	0	51	0	0
T152	47961	0	0	0
T153	14145	0	0	0
T154	107263	0	0	0
T155	3686	0	0	0
T156	7442	0	0	0
T157	31833	0	0	0
T158	200555	0	0	0
T159	186408	0	0	0
T160	59842	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397037409	2000	0	0
T101	2894	15	0	0
T102	1908	14	0	0
T103	11163	211	0	0
T104	6277	33	0	0
T105	2100	1	0	0
T106	2893	19	0	0
T107	2524	13	0	0
T108	4599	10	0	0
T109	2604	7	0	0
T110	3773	32	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397037409	2409	0	0
T101	2894	32	0	0
T102	1908	9	0	0
T103	11163	252	0	0
T104	6277	28	0	0
T105	2100	31	0	0
T106	2893	26	0	0
T107	2524	10	0	0
T108	4599	13	0	0
T109	2604	14	0	0
T110	3773	33	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397037409	1888	0	0
T101	2894	19	0	0
T102	1908	6	0	0
T103	11163	177	0	0
T104	6277	8	0	0
T105	2100	18	0	0
T106	2893	12	0	0
T108	4599	57	0	0
T109	2604	7	0	0
T110	3773	1	0	0
T127	2492	8	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397037409	2024	0	0
T101	2894	23	0	0
T102	1908	3	0	0
T103	11163	219	0	0
T104	6277	37	0	0
T105	2100	6	0	0
T107	2524	12	0	0
T108	4599	36	0	0
T109	2604	8	0	0
T110	3773	33	0	0
T127	2492	4	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397037409	1845	0	0
T101	2894	12	0	0
T102	1908	4	0	0
T103	11163	216	0	0
T104	6277	32	0	0
T105	2100	15	0	0
T106	2893	2	0	0
T107	2524	2	0	0
T108	4599	11	0	0
T109	2604	15	0	0
T110	3773	19	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397037409	1798	0	0
T101	2894	18	0	0
T102	1908	10	0	0
T103	11163	222	0	0
T104	6277	6	0	0
T105	2100	16	0	0
T106	2893	10	0	0
T107	2524	14	0	0
T108	4599	32	0	0
T109	2604	8	0	0
T110	3773	25	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397037409	1914	0	0
T101	2894	24	0	0
T102	1908	17	0	0
T103	11163	198	0	0
T104	6277	29	0	0
T105	2100	17	0	0
T106	2893	5	0	0
T107	2524	12	0	0
T108	4599	28	0	0
T109	2604	9	0	0
T110	3773	59	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397037409	1917	0	0
T101	2894	14	0	0
T102	1908	8	0	0
T103	11163	202	0	0
T104	6277	9	0	0
T105	2100	14	0	0
T106	2893	9	0	0
T107	2524	1	0	0
T108	4599	13	0	0
T109	2604	5	0	0
T110	3773	28	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397037409	1992	0	0
T101	2894	24	0	0
T102	1908	7	0	0
T103	11163	234	0	0
T104	6277	16	0	0
T105	2100	12	0	0
T106	2893	10	0	0
T107	2524	5	0	0
T108	4599	16	0	0
T109	2604	13	0	0
T110	3773	28	0	0