Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	31054870	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

8668696

1

T1

20

T2

30

T3

255

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	38863415	1			T1	43		T2	70		T3	774
values[0x0]	430138	1			T1	26		T2	38		T3	159
values[0x1]	430013	1			T1	28		T2	36		T3	147

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	21717837	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

18005729

1

T1

40

T2

56

T3

513

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	138534	1			T3	4		T4	632		T10	630
valid_sources[0x01]	140237	1			T3	6		T4	646		T10	695
valid_sources[0x02]	152706	1			T3	4		T4	633		T6	1
valid_sources[0x03]	150397	1			T2	2		T3	3		T4	638
valid_sources[0x04]	172981	1			T3	5		T4	649		T5	2
valid_sources[0x05]	184792	1			T3	3		T4	616		T6	1
valid_sources[0x06]	163894	1			T3	5		T4	687		T5	1
valid_sources[0x07]	154888	1			T3	4		T4	628		T6	1
valid_sources[0x08]	140122	1			T3	2		T4	648		T5	5
valid_sources[0x09]	145733	1			T3	4		T4	672		T5	1
valid_sources[0x0a]	150320	1			T3	2		T4	649		T9	1
valid_sources[0x0b]	147567	1			T3	4		T4	636		T10	680
valid_sources[0x0c]	166818	1			T2	3		T3	2		T4	689
valid_sources[0x0d]	161587	1			T3	4		T4	652		T5	2
valid_sources[0x0e]	137756	1			T3	6		T4	644		T5	3
valid_sources[0x0f]	142280	1			T3	1		T4	630		T5	2
valid_sources[0x10]	154617	1			T3	5		T4	641		T6	1
valid_sources[0x11]	159997	1			T3	3		T4	640		T5	2
valid_sources[0x12]	165157	1			T3	3		T4	655		T5	3
valid_sources[0x13]	159501	1			T3	3		T4	658		T5	2
valid_sources[0x14]	143721	1			T2	6		T3	2		T4	687
valid_sources[0x15]	163197	1			T3	4		T4	633		T5	1
valid_sources[0x16]	150826	1			T3	1		T4	654		T6	3
valid_sources[0x17]	163820	1			T2	2		T4	656		T10	754
valid_sources[0x18]	147434	1			T3	5		T4	676		T5	2
valid_sources[0x19]	167136	1			T3	1		T4	709		T10	775
valid_sources[0x1a]	147021	1			T3	5		T4	610		T5	2
valid_sources[0x1b]	152631	1			T2	3		T3	4		T4	686
valid_sources[0x1c]	154725	1			T3	4		T4	645		T5	2
valid_sources[0x1d]	159101	1			T3	4		T4	622		T6	1
valid_sources[0x1e]	152502	1			T3	2		T4	636		T10	775
valid_sources[0x1f]	150246	1			T3	5		T4	641		T10	736
valid_sources[0x20]	154709	1			T3	8		T4	642		T5	3
valid_sources[0x21]	164870	1			T3	4		T4	671		T5	3
valid_sources[0x22]	154614	1			T3	1		T4	631		T5	2
valid_sources[0x23]	165957	1			T3	2		T4	688		T6	1
valid_sources[0x24]	154805	1			T2	1		T3	5		T4	662
valid_sources[0x25]	143334	1			T3	1		T4	634		T5	3
valid_sources[0x26]	139768	1			T3	2		T4	648		T9	2
valid_sources[0x27]	165170	1			T3	12		T4	617		T6	1
valid_sources[0x28]	163759	1			T2	1		T3	6		T4	616
valid_sources[0x29]	142037	1			T2	2		T3	5		T4	746
valid_sources[0x2a]	142752	1			T3	7		T4	688		T9	2
valid_sources[0x2b]	139258	1			T2	3		T3	1		T4	682
valid_sources[0x2c]	144407	1			T3	3		T4	624		T5	1
valid_sources[0x2d]	163896	1			T3	5		T4	635		T5	3
valid_sources[0x2e]	164631	1			T3	4		T4	656		T9	1
valid_sources[0x2f]	139316	1			T3	5		T4	646		T6	1
valid_sources[0x30]	146385	1			T2	1		T3	3		T4	674
valid_sources[0x31]	161566	1			T3	2		T4	644		T5	2
valid_sources[0x32]	136906	1			T3	3		T4	631		T9	1
valid_sources[0x33]	153602	1			T2	3		T3	5		T4	693
valid_sources[0x34]	161924	1			T2	3		T3	5		T4	674
valid_sources[0x35]	157529	1			T3	1		T4	639		T6	1
valid_sources[0x36]	145157	1			T2	2		T3	1		T4	666
valid_sources[0x37]	179952	1			T3	7		T4	618		T10	794
valid_sources[0x38]	166202	1			T3	1		T4	679		T6	1
valid_sources[0x39]	151792	1			T3	1		T4	670		T8	1
valid_sources[0x3a]	152236	1			T3	4		T4	636		T5	1
valid_sources[0x3b]	150835	1			T2	2		T3	5		T4	653
valid_sources[0x3c]	130485	1			T2	1		T3	5		T4	664
valid_sources[0x3d]	159410	1			T3	2		T4	634		T5	1
valid_sources[0x3e]	142668	1			T3	4		T4	630		T10	870
valid_sources[0x3f]	145334	1			T3	2		T4	635		T6	1
valid_sources[0x40]	168171	1			T2	3		T4	650		T5	3
valid_sources[0x41]	150649	1			T3	7		T4	635		T9	1
valid_sources[0x42]	157116	1			T3	3		T4	694		T5	1
valid_sources[0x43]	148214	1			T3	8		T4	627		T6	1
valid_sources[0x44]	161320	1			T3	6		T4	686		T5	1
valid_sources[0x45]	155381	1			T3	5		T4	687		T6	1
valid_sources[0x46]	161908	1			T2	2		T3	4		T4	662
valid_sources[0x47]	160605	1			T3	2		T4	651		T5	3
valid_sources[0x48]	152652	1			T3	4		T4	648		T5	1
valid_sources[0x49]	153464	1			T3	4		T4	626		T5	1
valid_sources[0x4a]	158412	1			T3	1		T4	682		T5	1
valid_sources[0x4b]	155930	1			T3	2		T4	641		T10	748
valid_sources[0x4c]	155634	1			T3	4		T4	649		T5	2
valid_sources[0x4d]	154827	1			T3	5		T4	608		T5	1
valid_sources[0x4e]	159378	1			T3	4		T4	709		T10	592
valid_sources[0x4f]	154177	1			T3	1		T4	651		T5	1
valid_sources[0x50]	174019	1			T4	680		T5	1		T10	779
valid_sources[0x51]	165550	1			T3	3		T4	653		T9	2
valid_sources[0x52]	154117	1			T2	1		T3	5		T4	625
valid_sources[0x53]	142477	1			T3	4		T4	621		T5	1
valid_sources[0x54]	182244	1			T3	7		T4	643		T5	1
valid_sources[0x55]	148965	1			T3	2		T4	651		T5	1
valid_sources[0x56]	162582	1			T2	7		T3	7		T4	603
valid_sources[0x57]	173177	1			T3	2		T4	680		T6	1
valid_sources[0x58]	179699	1			T3	8		T4	643		T5	2
valid_sources[0x59]	155710	1			T3	5		T4	657		T8	4
valid_sources[0x5a]	170811	1			T3	5		T4	640		T5	2
valid_sources[0x5b]	159882	1			T3	7		T4	652		T6	1
valid_sources[0x5c]	147137	1			T2	2		T3	5		T4	682
valid_sources[0x5d]	156249	1			T3	4		T4	623		T5	1
valid_sources[0x5e]	167210	1			T3	3		T4	665		T5	1
valid_sources[0x5f]	151806	1			T3	4		T4	643		T5	4
valid_sources[0x60]	152896	1			T3	5		T4	666		T6	1
valid_sources[0x61]	154785	1			T3	5		T4	689		T5	3
valid_sources[0x62]	151719	1			T3	7		T4	640		T9	3
valid_sources[0x63]	174031	1			T2	4		T3	15		T4	657
valid_sources[0x64]	162066	1			T3	7		T4	680		T5	1
valid_sources[0x65]	147149	1			T3	7		T4	668		T10	802
valid_sources[0x66]	141021	1			T3	4		T4	616		T5	3
valid_sources[0x67]	169009	1			T3	2		T4	630		T5	1
valid_sources[0x68]	151209	1			T3	5		T4	653		T10	694
valid_sources[0x69]	153233	1			T3	6		T4	677		T5	1
valid_sources[0x6a]	146665	1			T3	7		T4	662		T10	792
valid_sources[0x6b]	156362	1			T3	4		T4	617		T5	1
valid_sources[0x6c]	166380	1			T2	2		T3	5		T4	647
valid_sources[0x6d]	146637	1			T3	1		T4	669		T10	739
valid_sources[0x6e]	149156	1			T3	6		T4	670		T6	2
valid_sources[0x6f]	153252	1			T2	11		T3	3		T4	662
valid_sources[0x70]	155103	1			T3	1		T4	659		T5	2
valid_sources[0x71]	176828	1			T3	3		T4	661		T5	1
valid_sources[0x72]	157464	1			T3	1		T4	635		T5	4
valid_sources[0x73]	167193	1			T3	5		T4	632		T6	1
valid_sources[0x74]	161315	1			T3	8		T4	649		T5	2
valid_sources[0x75]	201556	1			T3	2		T4	675		T5	1
valid_sources[0x76]	151213	1			T3	5		T4	662		T5	3
valid_sources[0x77]	145032	1			T3	2		T4	589		T5	2
valid_sources[0x78]	150674	1			T2	1		T3	1		T4	646
valid_sources[0x79]	165748	1			T2	2		T3	1		T4	632
valid_sources[0x7a]	167714	1			T3	4		T4	641		T5	1
valid_sources[0x7b]	142321	1			T3	3		T4	606		T5	1
valid_sources[0x7c]	149000	1			T2	2		T3	6		T4	642
valid_sources[0x7d]	157334	1			T3	5		T4	691		T5	1
valid_sources[0x7e]	159347	1			T3	7		T4	632		T5	3
valid_sources[0x7f]	155122	1			T3	4		T4	687		T10	698
valid_sources[0x80]	163585	1			T3	10		T4	641		T10	826

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

8290421

1

T1

2

T2

5

T3

124

values[0x0]

all_enables

biggest_size

225343

1

T1

8

T2

17

T3

83

values[0x1]

all_enables

biggest_size

152932

1

T1

10

T2

8

T3

48