Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.48	100.00	100.00	93.91			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	394390900	0	0	0
ctrl_rd_A	394390900	2143	0	0
host_fifo_config_rd_A	394390900	4622	0	0
host_nack_handler_timeout_rd_A	394390900	1228	0	0
host_timeout_ctrl_rd_A	394390900	988	0	0
intr_enable_rd_A	394390900	3654	0	0
ovrd_rd_A	394390900	2042	0	0
target_fifo_config_rd_A	394390900	1264	0	0
target_id_rd_A	394390900	1599	0	0
target_timeout_ctrl_rd_A	394390900	1257	0	0
timeout_ctrl_rd_A	394390900	1514	0	0
timing0_rd_A	394390900	1274	0	0
timing1_rd_A	394390900	1196	0	0
timing2_rd_A	394390900	1204	0	0
timing3_rd_A	394390900	1321	0	0
timing4_rd_A	394390900	1291	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394390900	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394390900	2143	0	0
T102	3244	23	0	0
T103	12653	101	0	0
T104	7514	153	0	0
T105	13155	45	0	0
T106	5445	104	0	0
T107	1767	43	0	0
T108	3184	9	0	0
T109	6088	92	0	0
T110	5031	6	0	0
T111	26350	230	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394390900	4622	0	0
T32	392732	144	0	0
T39	0	78	0	0
T45	108965	0	0	0
T56	53036	0	0	0
T58	869503	0	0	0
T77	74421	0	0	0
T78	141676	0	0	0
T112	0	134	0	0
T113	0	106	0	0
T114	0	187	0	0
T115	0	162	0	0
T116	0	153	0	0
T117	0	533	0	0
T118	0	189	0	0
T119	0	128	0	0
T120	12510	0	0	0
T121	17314	0	0	0
T122	1093	0	0	0
T123	141258	0	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394390900	1228	0	0
T102	3244	21	0	0
T103	12653	86	0	0
T104	7514	41	0	0
T105	13155	32	0	0
T106	5445	104	0	0
T107	1767	13	0	0
T108	3184	23	0	0
T109	6088	17	0	0
T110	5031	31	0	0
T111	26350	224	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394390900	988	0	0
T102	3244	20	0	0
T103	12653	29	0	0
T104	7514	34	0	0
T105	13155	21	0	0
T106	5445	107	0	0
T107	1767	13	0	0
T108	3184	5	0	0
T109	6088	10	0	0
T110	5031	19	0	0
T111	26350	241	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394390900	3654	0	0
T39	118972	2	0	0
T102	0	85	0	0
T103	0	307	0	0
T104	0	261	0	0
T117	0	29	0	0
T124	0	10	0	0
T125	0	23	0	0
T126	0	11	0	0
T127	0	19	0	0
T128	0	1	0	0
T129	828009	0	0	0
T130	47353	0	0	0
T131	50670	0	0	0
T132	11305	0	0	0
T133	22501	0	0	0
T134	128916	0	0	0
T135	7048	0	0	0
T136	13895	0	0	0
T137	46439	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394390900	2042	0	0
T52	11941	0	0	0
T85	1139	57	0	0
T101	0	17	0	0
T138	0	14	0	0
T139	0	38	0	0
T140	0	17	0	0
T141	0	26	0	0
T142	0	35	0	0
T143	0	39	0	0
T144	0	42	0	0
T145	0	44	0	0
T146	82972	0	0	0
T147	258904	0	0	0
T148	8221	0	0	0
T149	73468	0	0	0
T150	4121	0	0	0
T151	28106	0	0	0
T152	24312	0	0	0
T153	132250	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394390900	1264	0	0
T102	3244	23	0	0
T103	12653	44	0	0
T104	7514	55	0	0
T105	13155	23	0	0
T106	5445	99	0	0
T107	1767	16	0	0
T108	3184	11	0	0
T109	6088	59	0	0
T110	5031	20	0	0
T128	1805	3	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394390900	1599	0	0
T102	3244	12	0	0
T103	12653	99	0	0
T104	7514	99	0	0
T105	13155	9	0	0
T106	5445	117	0	0
T107	1767	2	0	0
T108	3184	11	0	0
T109	6088	37	0	0
T110	5031	60	0	0
T111	26350	207	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394390900	1257	0	0
T102	3244	26	0	0
T103	12653	81	0	0
T104	7514	57	0	0
T105	13155	25	0	0
T106	5445	101	0	0
T107	1767	13	0	0
T108	3184	29	0	0
T109	6088	65	0	0
T110	5031	19	0	0
T128	1805	5	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394390900	1514	0	0
T102	3244	25	0	0
T103	12653	69	0	0
T104	7514	80	0	0
T105	13155	29	0	0
T106	5445	97	0	0
T107	1767	22	0	0
T108	3184	26	0	0
T109	6088	68	0	0
T110	5031	56	0	0
T128	1805	4	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394390900	1274	0	0
T102	3244	26	0	0
T103	12653	63	0	0
T104	7514	43	0	0
T105	13155	22	0	0
T106	5445	105	0	0
T107	1767	8	0	0
T108	3184	10	0	0
T109	6088	49	0	0
T110	5031	92	0	0
T111	26350	201	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394390900	1196	0	0
T102	3244	9	0	0
T103	12653	67	0	0
T104	7514	54	0	0
T105	13155	29	0	0
T106	5445	110	0	0
T107	1767	7	0	0
T109	6088	10	0	0
T110	5031	39	0	0
T111	26350	202	0	0
T154	3252	14	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394390900	1204	0	0
T102	3244	16	0	0
T103	12653	45	0	0
T104	7514	45	0	0
T105	13155	31	0	0
T106	5445	63	0	0
T107	1767	2	0	0
T108	3184	34	0	0
T109	6088	33	0	0
T110	5031	67	0	0
T128	1805	3	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394390900	1321	0	0
T102	3244	6	0	0
T103	12653	82	0	0
T104	7514	56	0	0
T105	13155	53	0	0
T106	5445	112	0	0
T107	1767	4	0	0
T108	3184	10	0	0
T109	6088	35	0	0
T110	5031	32	0	0
T128	1805	6	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394390900	1291	0	0
T102	3244	19	0	0
T103	12653	50	0	0
T104	7514	62	0	0
T105	13155	43	0	0
T106	5445	104	0	0
T107	1767	8	0	0
T108	3184	17	0	0
T109	6088	42	0	0
T110	5031	11	0	0
T128	1805	6	0	0