Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.14	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	7	53	88.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	7	53	88.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	772561	1			T1	2		T2	2		T3	2
all_values[1]	772561	1			T1	2		T2	2		T3	2
all_values[2]	772561	1			T1	2		T2	2		T3	2
all_values[3]	772561	1			T1	2		T2	2		T3	2
all_values[4]	772561	1			T1	2		T2	2		T3	2
all_values[5]	772561	1			T1	2		T2	2		T3	2
all_values[6]	772561	1			T1	2		T2	2		T3	2
all_values[7]	772561	1			T1	2		T2	2		T3	2
all_values[8]	772561	1			T1	2		T2	2		T3	2
all_values[9]	772561	1			T1	2		T2	2		T3	2
all_values[10]	772561	1			T1	2		T2	2		T3	2
all_values[11]	772561	1			T1	2		T2	2		T3	2
all_values[12]	772561	1			T1	2		T2	2		T3	2
all_values[13]	772561	1			T1	2		T2	2		T3	2
all_values[14]	772561	1			T1	2		T2	2		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9539090

1

T1

24

T2

26

T3

26

auto[1]

2049325

1

T1

6

T2

4

T3

4

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10896425

1

T1

30

T2

30

T3

30

auto[1]

691990

1

T18

8257

T29

240975

T166

3760

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	7	53	88.33	7

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[3]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[5] , all_values[6]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[8]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	101883	1			T7	1		T14	11		T11	4
all_values[0]	auto[0]	auto[1]	4519	1			T18	19		T29	1197		T166	14
all_values[0]	auto[1]	auto[0]	627686	1			T1	2		T2	2		T3	2
all_values[0]	auto[1]	auto[1]	38473	1			T18	532		T29	16015		T166	328
all_values[1]	auto[0]	auto[0]	724106	1			T1	2		T2	2		T3	2
all_values[1]	auto[0]	auto[1]	47939	1			T18	546		T29	17210		T227	5
all_values[1]	auto[1]	auto[0]	341	1			T15	35		T32	1		T22	8
all_values[1]	auto[1]	auto[1]	175	1			T18	4		T29	1		T227	1
all_values[2]	auto[0]	auto[0]	723071	1			T1	1		T2	2		T3	2
all_values[2]	auto[0]	auto[1]	49139	1			T18	543		T29	17212		T227	3
all_values[2]	auto[1]	auto[0]	193	1			T1	1		T10	1		T64	1
all_values[2]	auto[1]	auto[1]	158	1			T18	7		T29	1		T227	1
all_values[3]	auto[0]	auto[0]	724617	1			T1	2		T2	2		T3	2
all_values[3]	auto[0]	auto[1]	47773	1			T18	542		T29	17211		T166	338
all_values[3]	auto[1]	auto[1]	171	1			T18	7		T29	1		T166	4
all_values[4]	auto[0]	auto[0]	723235	1			T1	2		T2	2		T3	2
all_values[4]	auto[0]	auto[1]	49127	1			T18	545		T29	17210		T227	3
all_values[4]	auto[1]	auto[0]	22	1			T22	1		T24	1		T256	2
all_values[4]	auto[1]	auto[1]	177	1			T18	5		T29	3		T227	1
all_values[5]	auto[0]	auto[0]	729557	1			T1	2		T2	2		T3	2
all_values[5]	auto[0]	auto[1]	42815	1			T18	545		T29	17211		T166	339
all_values[5]	auto[1]	auto[1]	189	1			T18	6		T29	1		T166	3
all_values[6]	auto[0]	auto[0]	722923	1			T1	2		T2	2		T3	2
all_values[6]	auto[0]	auto[1]	49455	1			T18	543		T29	17211		T166	338
all_values[6]	auto[1]	auto[1]	183	1			T18	8		T29	2		T166	3
all_values[7]	auto[0]	auto[0]	698526	1			T1	2		T2	2		T3	2
all_values[7]	auto[0]	auto[1]	44931	1			T18	537		T29	16670		T166	288
all_values[7]	auto[1]	auto[0]	26079	1			T11	1		T15	226		T31	143
all_values[7]	auto[1]	auto[1]	3025	1			T18	14		T29	543		T166	54
all_values[8]	auto[0]	auto[0]	724093	1			T1	2		T2	2		T3	2
all_values[8]	auto[0]	auto[1]	48249	1			T18	538		T29	17209		T166	338
all_values[8]	auto[1]	auto[1]	219	1			T18	13		T29	3		T166	4
all_values[9]	auto[0]	auto[0]	179698	1			T1	2		T2	2		T3	2
all_values[9]	auto[0]	auto[1]	11262	1			T18	538		T29	865		T166	316
all_values[9]	auto[1]	auto[0]	544394	1			T5	1		T64	1		T46	1
all_values[9]	auto[1]	auto[1]	37207	1			T18	10		T29	16348		T166	26
all_values[10]	auto[0]	auto[0]	723507	1			T1	2		T2	2		T3	2
all_values[10]	auto[0]	auto[1]	48882	1			T18	544		T29	17211		T166	339
all_values[10]	auto[1]	auto[1]	172	1			T18	7		T29	2		T166	3
all_values[11]	auto[0]	auto[0]	2414	1			T7	1		T14	11		T11	4
all_values[11]	auto[0]	auto[1]	316	1			T18	11		T166	3		T227	3
all_values[11]	auto[1]	auto[0]	737705	1			T1	2		T2	2		T3	2
all_values[11]	auto[1]	auto[1]	32126	1			T18	540		T166	339		T227	3
all_values[12]	auto[0]	auto[0]	723203	1			T1	1		T2	2		T3	2
all_values[12]	auto[0]	auto[1]	49126	1			T18	544		T29	17210		T227	4
all_values[12]	auto[1]	auto[0]	66	1			T1	1		T10	1		T62	1
all_values[12]	auto[1]	auto[1]	166	1			T18	7		T29	3		T227	2
all_values[13]	auto[0]	auto[0]	729550	1			T1	2		T2	2		T3	2
all_values[13]	auto[0]	auto[1]	42816	1			T18	549		T29	17209		T166	338
all_values[13]	auto[1]	auto[1]	195	1			T18	2		T29	4		T166	3
all_values[14]	auto[0]	auto[0]	729556	1			T1	2		T2	2		T3	2
all_values[14]	auto[0]	auto[1]	42802	1			T18	543		T29	17211		T166	339
all_values[14]	auto[1]	auto[1]	203	1			T18	8		T29	1		T166	3