| | | | | | | | |
tb |
91.43 |
97.21 |
89.42 |
97.22 |
72.02 |
94.26 |
98.44 |
| dut |
91.43 |
97.21 |
89.42 |
97.22 |
72.02 |
94.26 |
98.44 |
| gen_alert_tx[0].u_prim_alert_sender |
100.00 |
|
|
100.00 |
|
|
|
| i2c_core |
87.63 |
96.20 |
83.68 |
|
72.02 |
91.56 |
94.69 |
| intr_hw_acq_overflow |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
| intr_hw_acq_threshold |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
| intr_hw_cmd_complete |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
| intr_hw_controller_halt |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
| intr_hw_fmt_threshold |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
| intr_hw_host_timeout |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
| intr_hw_rx_overflow |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
| intr_hw_rx_threshold |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
| intr_hw_scl_interference |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
| intr_hw_sda_interference |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
| intr_hw_sda_unstable |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
| intr_hw_stretch_timeout |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
| intr_hw_tx_stretch |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
| intr_hw_tx_threshold |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
| intr_hw_unexp_stop |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
| u_fifos |
93.75 |
99.86 |
83.33 |
|
|
98.32 |
93.48 |
| u_acq_fifo_sram_adapter |
95.85 |
100.00 |
84.91 |
|
|
98.51 |
100.00 |
| u_inp_buf |
94.32 |
100.00 |
81.82 |
|
|
95.45 |
100.00 |
| gen_normal_fifo.u_fifo_cnt |
94.10 |
100.00 |
90.00 |
|
|
92.31 |
|
| u_oup_buf |
97.73 |
100.00 |
90.91 |
|
|
100.00 |
100.00 |
| gen_normal_fifo.u_fifo_cnt |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| u_sram_ptrs |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| u_fmt_fifo_sram_adapter |
95.54 |
100.00 |
83.65 |
|
|
98.51 |
100.00 |
| u_inp_buf |
94.32 |
100.00 |
81.82 |
|
|
95.45 |
100.00 |
| gen_normal_fifo.u_fifo_cnt |
94.10 |
100.00 |
90.00 |
|
|
92.31 |
|
| u_oup_buf |
97.16 |
100.00 |
88.64 |
|
|
100.00 |
100.00 |
| gen_normal_fifo.u_fifo_cnt |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| u_sram_ptrs |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| u_ram_1p |
99.02 |
97.06 |
|
|
|
100.00 |
100.00 |
| u_mem |
95.24 |
85.71 |
|
|
|
100.00 |
100.00 |
| gen_generic.u_impl_generic |
95.24 |
85.71 |
|
|
|
100.00 |
100.00 |
| u_req_d_buf |
100.00 |
100.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
| u_write_d_buf |
100.00 |
100.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
| u_ram_arbiter |
90.93 |
100.00 |
82.46 |
|
|
100.00 |
81.25 |
| u_rx_fifo_sram_adapter |
94.69 |
100.00 |
81.76 |
|
|
97.01 |
100.00 |
| u_inp_buf |
90.91 |
100.00 |
72.73 |
|
|
90.91 |
100.00 |
| gen_normal_fifo.u_fifo_cnt |
88.21 |
100.00 |
80.00 |
|
|
84.62 |
|
| u_oup_buf |
97.16 |
100.00 |
88.64 |
|
|
100.00 |
100.00 |
| gen_normal_fifo.u_fifo_cnt |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| u_sram_ptrs |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| u_tx_fifo_sram_adapter |
95.54 |
100.00 |
83.65 |
|
|
98.51 |
100.00 |
| u_inp_buf |
94.32 |
100.00 |
81.82 |
|
|
95.45 |
100.00 |
| gen_normal_fifo.u_fifo_cnt |
94.10 |
100.00 |
90.00 |
|
|
92.31 |
|
| u_oup_buf |
97.16 |
100.00 |
88.64 |
|
|
100.00 |
100.00 |
| gen_normal_fifo.u_fifo_cnt |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| u_sram_ptrs |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| u_i2c_bus_monitor |
89.50 |
96.26 |
90.32 |
|
81.82 |
89.58 |
|
| u_i2c_controller_fsm |
83.78 |
90.34 |
76.64 |
|
66.67 |
85.25 |
100.00 |
| u_i2c_sync_scl |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_i2c_sync_sda |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_i2c_target_fsm |
86.20 |
93.80 |
80.00 |
|
73.58 |
83.64 |
100.00 |
| i2c_csr_assert |
93.75 |
|
|
|
|
|
93.75 |
| tlul_assert_device |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
| u_reg |
98.67 |
98.59 |
97.16 |
100.00 |
|
97.58 |
100.00 |
| subtree... |
|
|
|
|
|
|
|