Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	772561	1			T1	2		T2	2		T3	2
all_pins[1]	772561	1			T1	2		T2	2		T3	2
all_pins[2]	772561	1			T1	2		T2	2		T3	2
all_pins[3]	772561	1			T1	2		T2	2		T3	2
all_pins[4]	772561	1			T1	2		T2	2		T3	2
all_pins[5]	772561	1			T1	2		T2	2		T3	2
all_pins[6]	772561	1			T1	2		T2	2		T3	2
all_pins[7]	772561	1			T1	2		T2	2		T3	2
all_pins[8]	772561	1			T1	2		T2	2		T3	2
all_pins[9]	772561	1			T1	2		T2	2		T3	2
all_pins[10]	772561	1			T1	2		T2	2		T3	2
all_pins[11]	772561	1			T1	2		T2	2		T3	2
all_pins[12]	772561	1			T1	2		T2	2		T3	2
all_pins[13]	772561	1			T1	2		T2	2		T3	2
all_pins[14]	772561	1			T1	2		T2	2		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	9544788	1			T1	27		T2	26		T3	26
values[0x1]	2043627	1			T1	3		T2	4		T3	4
transitions[0x0=>0x1]	2042836	1			T1	3		T2	4		T3	4
transitions[0x1=>0x0]	2041522	1			T1	3		T2	3		T3	3

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	109782	1			T1	1		T7	1		T10	1
all_pins[0]	values[0x1]	662779	1			T1	1		T2	2		T3	2
all_pins[0]	transitions[0x0=>0x1]	662325	1			T1	1		T2	2		T3	2
all_pins[0]	transitions[0x1=>0x0]	66	1			T22	8		T227	1		T101	1
all_pins[1]	values[0x0]	772041	1			T1	2		T2	2		T3	2
all_pins[1]	values[0x1]	520	1			T15	42		T32	1		T22	8
all_pins[1]	transitions[0x0=>0x1]	498	1			T15	42		T32	1		T22	8
all_pins[1]	transitions[0x1=>0x0]	110	1			T64	1		T267	1		T18	6
all_pins[2]	values[0x0]	772429	1			T1	2		T2	2		T3	2
all_pins[2]	values[0x1]	132	1			T64	1		T267	1		T18	6
all_pins[2]	transitions[0x0=>0x1]	115	1			T64	1		T267	1		T18	5
all_pins[2]	transitions[0x1=>0x0]	67	1			T18	2		T29	1		T166	2
all_pins[3]	values[0x0]	772477	1			T1	2		T2	2		T3	2
all_pins[3]	values[0x1]	84	1			T18	3		T29	1		T166	2
all_pins[3]	transitions[0x0=>0x1]	63	1			T18	1		T29	1		T166	2
all_pins[3]	transitions[0x1=>0x0]	95	1			T22	1		T18	2		T29	1
all_pins[4]	values[0x0]	772445	1			T1	2		T2	2		T3	2
all_pins[4]	values[0x1]	116	1			T22	1		T18	4		T29	1
all_pins[4]	transitions[0x0=>0x1]	102	1			T22	1		T18	4		T29	1
all_pins[4]	transitions[0x1=>0x0]	76	1			T18	2		T29	1		T268	3
all_pins[5]	values[0x0]	772471	1			T1	2		T2	2		T3	2
all_pins[5]	values[0x1]	90	1			T18	2		T29	1		T268	4
all_pins[5]	transitions[0x0=>0x1]	71	1			T18	1		T29	1		T268	4
all_pins[5]	transitions[0x1=>0x0]	68	1			T18	5		T29	1		T268	3
all_pins[6]	values[0x0]	772474	1			T1	2		T2	2		T3	2
all_pins[6]	values[0x1]	87	1			T18	6		T29	1		T268	3
all_pins[6]	transitions[0x0=>0x1]	71	1			T18	3		T29	1		T268	2
all_pins[6]	transitions[0x1=>0x0]	31795	1			T11	1		T15	295		T31	154
all_pins[7]	values[0x0]	740750	1			T1	2		T2	2		T3	2
all_pins[7]	values[0x1]	31811	1			T11	1		T15	295		T31	154
all_pins[7]	transitions[0x0=>0x1]	31787	1			T11	1		T15	295		T31	154
all_pins[7]	transitions[0x1=>0x0]	78	1			T18	4		T29	1		T227	1
all_pins[8]	values[0x0]	772459	1			T1	2		T2	2		T3	2
all_pins[8]	values[0x1]	102	1			T18	7		T29	3		T227	1
all_pins[8]	transitions[0x0=>0x1]	83	1			T18	4		T29	2		T227	1
all_pins[8]	transitions[0x1=>0x0]	581499	1			T5	1		T64	1		T46	1
all_pins[9]	values[0x0]	191043	1			T1	2		T2	2		T3	2
all_pins[9]	values[0x1]	581518	1			T5	1		T64	1		T46	1
all_pins[9]	transitions[0x0=>0x1]	581492	1			T5	1		T64	1		T46	1
all_pins[9]	transitions[0x1=>0x0]	60	1			T18	1		T29	1		T166	1
all_pins[10]	values[0x0]	772475	1			T1	2		T2	2		T3	2
all_pins[10]	values[0x1]	86	1			T18	2		T29	1		T166	2
all_pins[10]	transitions[0x0=>0x1]	64	1			T18	2		T29	1		T101	1
all_pins[10]	transitions[0x1=>0x0]	765921	1			T1	1		T2	2		T3	2
all_pins[11]	values[0x0]	6618	1			T1	1		T7	1		T10	1
all_pins[11]	values[0x1]	765943	1			T1	1		T2	2		T3	2
all_pins[11]	transitions[0x0=>0x1]	765900	1			T1	1		T2	2		T3	2
all_pins[11]	transitions[0x1=>0x0]	117	1			T1	1		T10	1		T62	1
all_pins[12]	values[0x0]	772401	1			T1	1		T2	2		T3	2
all_pins[12]	values[0x1]	160	1			T1	1		T10	1		T62	1
all_pins[12]	transitions[0x0=>0x1]	142	1			T1	1		T10	1		T62	1
all_pins[12]	transitions[0x1=>0x0]	75	1			T29	2		T227	1		T268	3
all_pins[13]	values[0x0]	772468	1			T1	2		T2	2		T3	2
all_pins[13]	values[0x1]	93	1			T18	2		T29	3		T227	1
all_pins[13]	transitions[0x0=>0x1]	63	1			T18	1		T29	3		T227	1
all_pins[13]	transitions[0x1=>0x0]	76	1			T18	1		T29	1		T166	2
all_pins[14]	values[0x0]	772455	1			T1	2		T2	2		T3	2
all_pins[14]	values[0x1]	106	1			T18	2		T29	1		T166	2
all_pins[14]	transitions[0x0=>0x1]	60	1			T18	2		T29	1		T166	1
all_pins[14]	transitions[0x1=>0x0]	661419	1			T1	1		T2	1		T3	1